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Low Power CMOS SRAM
256K X 16
UC62LV4096
-55/-70
AC ELECTRICAL CHARACTERISTICS (TA=0℃ to 70℃, VCC=1.5V~3.6V)
WRITE CYCLE
UC62LV4096-55
UC62LV4096-70
JEDEC
PARAMETER
NAME
PARAMETER
NAME
DESCRIPTION
Min
Typ
Max
Min
Typ
Max
UNIT
tAVAX
tWC
Write Cycle Time
55
-
-
70
-
-
ns
tE1LWH
tCW
Chip Select to END of Write
40
-
-
50
-
-
ns
tAVWL
tAS
Address Setup Time
0
-
-
0
-
-
ns
tAVWH
tAW
Address valid to End of Write
40
-
-
50
-
-
ns
tBW
tBW
Data Byte Control End of Write
40
50
Ns
tWLWH
tWP
Write Pulse Width
40
-
-
50
-
-
ns
tWHAX
tWR
Write Recovery Time
0
-
-
0
-
-
ns
tWLOZ
tWHZ
Write to Output in High Z
-
-
20
-
-
20
ns
tDVWH
tDW
Data to Write Time Overlap
35
-
40
-
ns
tWHDX
tDH
Data Hold Time for Write End
0
-
-
0
-
-
ns
tGHOZ
tOHZ
Output Disable to Output In High Z
-
-
20
-
-
20
ns
tWHQX
tOW
End of Write to Output Active
10
-
-
10
-
-
ns
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITECYCLE1
(1)
t
WC
ADDRESS
t
DH
t
OHZ
WE
D
OUT
OE
CE
t
CW
(11)
t
WP
(2)
t
AW
t
AS
(4,10)
D
IN
t
DW
t
BW
UB/LB
U-Chip Technology Corp. LTD.
Preliminary
Rev. 1.0
Reserves the right to modify document contents without notice.
PAGE 6