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MTC20455MB-I Datasheet(PDF) 8 Page - STMicroelectronics |
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MTC20455MB-I Datasheet(HTML) 8 Page - STMicroelectronics |
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8 / 23 page  MTC20455 8/23 F4 VDD P VSS+1.8V F1 AD_12 B BD8STARP_TC Address/Data Bus G2 AD_13 B BD8STARP_TC Address/Data Bus G3 AD_14 B BD8STARP_TC Address/Data Bus G4 AD_15 B BD8STARP_TC Address/Data Bus G1 VSS G H2 PCLK I TLCHT_TC Processor Clock H3 BE I TLCHT_TC Address bit 1 H1 ALE I TLCHT_TC Address Latch J2 CSB_0 I TLCHT_TC Chip select line 0 H4 VDD P VSS+1.8V J3 CSB_1 I TLCHT_TC Chip select line 1 J1 CSB_2 I TLCHT_TC Chip select line 2 K2 CSB_3 I TLCHT_TC Chip select line 3 J4 WR_RDB I TLCHT_TC Write/Not read K3 VSS G K1 RDYB OZ BD4STARP_TC Ready indication L2 OBC_TYPE I-PD TLCHTDQ_TC I960/Generic selection L3 INTB_0 O BD4STARP_TC Requests OBC interrupt service line 0 L1 INTB_1 O BD4STARP_TC Requests OBC interrupt service line 1 K4 VDD P VSS+1.8V M2 INTB_2 O BD4STARP_TC Requests OBC interrupt service line 2 M1 INTB_3 O BD4STARP_TC Requests OBC interrupt service line 3 N2 RESETB I TLCHT_TC Hard reset N1 VSS G P1 VDD P VSS+1.8V P2 TDO OZ BD4STARP_TC Boundary scan out M3 TDI I-PU TLCHTUQ_TC Boundary scan in N3 TMS I-PU TLCHTUQ_TC Tap controller signal L4 TCK I-PD TLCHTDQ_TC Boundary scan clock P3 TRSTB I-PD TLCHTDQ_TC Not reset of Tap controller M4 VSS G N4 TESTE I-PD TLCHTDQ_TC Enables scan test mode P4 VSSIO G L5 U_RXDATA_0 OZ BD8STARP_TC Utopia receive data bus M5 U_RXDATA_1 OZ BD8STARP_TC Utopia receive data bus N5 U_RXDATA_2 OZ BD8STARP_TC Utopia receive data bus P5 U_RXDATA_3 OZ BD8STARP_TC Utopia receive data bus L6 U_RXDATA_4 OZ BD8STARP_TC Utopia receive data bus M6 U_RXDATA_5 OZ BD8STARP_TC Utopia receive data bus N6 U_RXDATA_6 OZ BD8STARP_TC Utopia receive data bus P6 U_RXDATA_7 OZ BD8STARP_TC Utopia receive data bus L7 VDDIO P VSSIO+3.3V Table 4. LFBGA 160 pin list (continued) Pin # Signal Name Signal type Technology Description |
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