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MPC826XACZUXXXX Datasheet(PDF) 5 Page - Motorola, Inc |
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MPC826XACZUXXXX Datasheet(HTML) 5 Page - Motorola, Inc |
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5 / 48 page  MOTOROLA MPC826xA (HiP4) Family Hardware Specifications 5 PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Features — Interfaces to G2 core through on-chip 32-Kbyte dual-port RAM and DMA controller — Serial DMA channels for receive and transmit on all serial channels — Parallel I/O registers with open-drain and interrupt capability — Virtual DMA functionality executing memory-to-memory and memory-to-I/O transfers — Three fast communications controllers supporting the following protocols: – 10/100-Mbit Ethernet/IEEE 802.3 CDMA/CS interface through media independent interface (MII) – ATM—Full-duplex SAR protocols at 155 Mbps, through UTOPIA interface, AAL5, AAL1, AAL0 protocols, TM 4.0 CBR, VBR, UBR, ABR traffic types, up to 16 K external connections – Transparent – HDLC—Up to T3 rates (clear channel) — Two multichannel controllers (MCCs) – Each MCC handles 128 serial, full-duplex, 64-Kbps data channels.Each MCC can be split into four subgroups of 32 channels each. – Almost any combination of subgroups can be multiplexed to single or multiple TDM interfaces up to four TDM interfaces per MCC — Four serial communications controllers (SCCs) identical to those on the MPC860, supporting the digital portions of the following protocols: – Ethernet/IEEE 802.3 CDMA/CS – HDLC/SDLC and HDLC bus – Universal asynchronous receiver transmitter (UART) – Synchronous UART – Binary synchronous (BISYNC) communications – Transparent — Two serial management controllers (SMCs), identical to those of the MPC860 – Provide management for BRI devices as general circuit interface (GCI) controllers in time- division-multiplexed (TDM) channels – Transparent – UART (low-speed operation) — One serial peripheral interface identical to the MPC860 SPI — One inter-integrated circuit (I2C) controller (identical to the MPC860 I2C controller) – Microwire compatible – Multiple-master, single-master, and slave modes — Up to eight TDM interfaces – Supports two groups of four TDM channels for a total of eight TDMs – 2,048 bytes of SI RAM – Bit or byte resolution – Independent transmit and receive routing, frame synchronization |
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