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HDMP-2634 Datasheet(PDF) 1 Page - Agilent(Hewlett-Packard)

Part # HDMP-2634
Description  2.5/1.25 GBd Serdes Circuit
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Manufacturer  HP [Agilent(Hewlett-Packard)]
Direct Link  http://www.home.agilent.com
Logo HP - Agilent(Hewlett-Packard)

HDMP-2634 Datasheet(HTML) 1 Page - Agilent(Hewlett-Packard)

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Agilent HDMP-2634
2.5/1.25 GBd Serdes Circuit
Data Sheet
Features
• 10-bit wide parallel Tx, Rx busses
• 125 MHz TBC and RBC[0:1]
• Option to set Tx and Rx serial
data rates separately
• Parallel data I/O, clocks and
control compatible with SSTL_2
• Differential PECL or LVTTL REFCLK
at 125 MHz
• Double data rate transfers
• Source synchronous clocking of
transmit data
• Source centered or source
synchronous clocking of
receive data
• Dual or single receive byte
clocks
• Parallel loopback mode
• Differential BLL serial I/O with
on-chip source termination
• 14 mm, 64-pin MQFP package
• Single +3.3 V power supply
Applications
• Gigabit ethernet channel
aggregation trunks
• Fast serial backplanes
• Clusters
Ordering Information
Part Number
Parallel I/O
HDMP-2634
SSTL_2
Description
This data sheet describes the
HDMP-2634 Serdes device for
2.5 GBd serial data rates.
The HDMP-2634 Serdes is a silicon
bipolar integrated circuit in a metal-
lized QFP package. It provides a
low-cost physical layer solution for
2.5 GBd serial link interfaces includ-
ing a complete Serialize/Deserialize
(Serdes) function with transmit and
receive sections in a single device.
The HDMP-2634 is also capable of
operating on 1.25 GBd serial links.
Input pins TX_RATE and RX_RATE
select the data rates on the transmit
and receive sides, respectively.
As shown in Figure 1, the transmit-
ter section accepts 10-bit wide par-
allel SSTL_2 data (TX[0:9]) and a
125 MHz SSTL_2 byte clock (TBC)
and serializes them into a high-
speed serial stream. The parallel
data is expected to be “8B/10B”
encoded data or equivalent. At the
source, TX[0:9] and TBC switch
synchronously with respect to a 125
MHz clock internal to the sender.
New data are emitted on both edges
of TBC; this is called Double Data
Rate (DDR). The HDMP-2634 finds
a sampling window between the
two edges of TBC to latch TX[0:9]
data into the input register of the
transmitter section when
TX_RATE=1. If TX_RATE=0, the
user must ensure no data transi-
tions on the falling edge of TBC
and this edge is used to latch in
parallel data resulting in a 1.25
GBd serial stream.
The transmitter section’s PLL
locks to the 125 MHz TBC. This
clock is then multiplied by 20 to
generate the 2500 MHz serial
clock for the high-speed serial
outputs. The high-speed outputs
are capable of interfacing directly
to copper cables or PCB traces
for electrical transmission or to
a separate fiber optic module
for optical transmission. The
high-speed outputs include user-
controllable skin-loss equalization
to improve performance when
driving copper lines.
The receiver section accepts a
serial electrical data stream at
1.25 or 2.5 GBd and recovers
10-bit wide parallel data. The
receiver PLL locks onto the incom-
ing serial signal and recovers the


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