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PE9704ES Datasheet(PDF) 3 Page - Peregrine Semiconductor Corp. |
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PE9704ES Datasheet(HTML) 3 Page - Peregrine Semiconductor Corp. |
3 / 11 page PE9704 Advance Information PEREGRINE SEMICONDUCTOR CORP. | http://www.peregrine-semi.com Copyright Peregrine Semiconductor Corp. 2003 Page 3 of 12 Pin No. Pin Name Interface Mode Type Description M5 Direct Input M Counter bit5 17 GND Both Ground CLOCK Serial Input Clock input. Data is clocked serially into either the 20-bit primary register (E_WR “low”) or the 8-bit enhancement register (E_WR “high”) on the rising edge of CLOCK. 18 M6 Direct Input M Counter bit6 19 M7 Direct Input M Counter bit7 20 M8 Direct Input M Counter bit8 (MSB) 21 A0 Direct Input A Counter bit0 22 DMODE Both Input Selects direct interface mode (DMODE=1) or serial interface mode (DMODE=0) 23 VDD Both (Note 1) Same as pin 1 E_WR Serial Input Enhancement register write enable. While E_WR is “high”, DATA can be serially clocked into the enhancement register on the rising edge of CLOCK. 24 A1 Direct Input A Counter bit1. 25 A2 Direct Input A Counter bit2 26 A3 Direct Input A Counter bit3 (MSB) 27 FIN Both Input RF prescaler input from the VCO. 3.0 GHz maximum frequency. 28 GND Both Ground. 29 GND Both Ground. 30 N/C No connect. 31 VDD Both (Note 1) Same as pin 1 32 DOUT Serial Output Data Out. The Main Counter output, R Counter output, or dual modulus prescaler select (MSEL) can be routed to DOUT through enhancement register programming. 33 VDD Both (Note 1) Same as pin 1 34 N/C No connect. 35 GND Both Ground. 36 PD_D Both Output PD_D pulses down when fp leads fc. 37 PD_U Both PD_U pulses down when fc leads fp. 38 VDD Both (Note 1) Same as pin 1 39 CEXT Both Output Logical “NAND” of PD_U and PD_D, passed through an on-chip, 2 k Ω series resistor. Connecting CEXT to an external capacitor will low pass filter the input to the inverting amplifier used for driving LD. 40 GND Both Ground 41 GND Both Ground 42 FR Both Input Reference frequency input 43 ENH Both Output, OD Enhancement mode. When asserted low (“0”), enhancement register bits are functional. 44 LD Serial Output Lock detect output, the open-drain logical inversion of CEXT. When the loop is locked, LD is high impedance; otherwise LD is a logic low (“0”). Note 1: VDD pins 1, 11, 12, 23, 31, 33, 35, and 38 are connected by diodes and must be supplied with the same positive voltage level. Note 2: All digital input pins have 70 k Ω pull-down resistors to ground. |
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