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PE83336EK Datasheet(PDF) 10 Page - Peregrine Semiconductor Corp. |
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PE83336EK Datasheet(HTML) 10 Page - Peregrine Semiconductor Corp. |
10 / 14 page PE83336 Product Specification Copyright Peregrine Semiconductor Corp. 2003 File No. 70/0137~01A | UTSi CMOS RFIC SOLUTIONS Page 10 of 14 inadvertent control changes during serial loading, with buffer capture of the serially entered data performed on the falling edge of E_WR according to the timing diagram shown in Figure 5. After the falling edge of E_WR, the data provide control bits as shown in Table 8 with bit functionality enabled by asserting the Enh input “low”. Direct Interface Mode Direct Interface Mode is selected by setting the Bmode input “high”. Counter control bits are set directly at the pins as shown in Table 7. In Direct Interface Mode, main counter inputs M7 and M8, and R Counter inputs R4 and R5 are internally forced low (“0”). Table 8. Primary Register Programming Interface Mode Enh Bmode Smode R5 R4 M8 M7 Pre_en M6 M5 M4 M3 M2 M1 M0 R3 R2 R1 R0 A3 A2 A1 A0 M2_WR rising edge load M1_WR rising edge load A_WR rising edge load Parallel 1 0 0 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Serial* 1 0 1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 Direct 1 1 X 0 0 0 0 Pre_en M6 M5 M4 M3 M2 M1 M0 R3 R2 R1 R0 A3 A2 A1 A0 *Serial data clocked serially on Sclk rising edge while E_WR “low” and captured in secondary register on S_WR rising edge. MSB (first in) (last in) LSB Table 9. Enhancement Register Programming Interface Mode Enh Bmode Smode Reserved Reserved Reserved Power down Counter load MSEL output Prescaler output fc, fp OE E_WR rising edge load Parallel 0 X 0 D7 D6 D5 D4 D3 D2 D1 D0 Serial* 0 X 1 B0 B1 B2 B3 B4 B5 B6 B7 *Serial data clocked serially on Sclk rising edge while E_WR “high” and captured in the double buffer on E_WR falling edge. MSB (first in) (last in) LSB |
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