PE83336

Product Specification

Copyright

File No. 70/0137~01A



CMOS RFIC SOLUTIONS

Page 10 of 14

inadvertent control changes during serial loading,

with buffer capture of the serially entered data

performed on the falling edge of E_WR according to

the timing diagram shown in Figure 5. After the

falling edge of E_WR, the data provide control bits

as shown in Table 8 with bit functionality enabled by

asserting the Enh input “low”.

Direct Interface Mode

Direct Interface Mode is selected by setting the

Bmode input “high”.

Counter control bits are set directly at the pins as

shown in Table 7. In Direct Interface Mode, main

Table 8. Primary Register Programming

Interface

Mode

Enh

Bmode Smode

M2_WR rising edge load

M1_WR rising edge load

A_WR rising edge load

Parallel

1

0

0

Serial*

1

0

1

Direct

1

1

X

0

0

0

0

*Serial data clocked serially on Sclk rising edge while E_WR “low” and captured in secondary register on S_WR rising edge.

MSB (first in)

(last in) LSB

Table 9. Enhancement Register Programming

Interface

Mode

Enh

Bmode Smode

Reserved

Reserved

Reserved

Power

down

Counter

load

MSEL

output

Prescaler

output

E_WR rising edge load

Parallel

0

X

0

Serial*

0

X

1

*Serial data clocked serially on Sclk rising edge while E_WR “high” and captured in the double buffer on E_WR falling edge.

MSB (first in)

(last in) LSB