ELECTRONICS

KM62V256C, KM62U256C Family

CMOS SRAM

Revision 04

April 1996

- 8 -

Address

/WE

Data in

/CS

Data out

Data Valid

Data Undefined

Address

/CS

/WE

Data in

Data out

Data Valid

High - Z

High - Z

DH

t

Notes (WRITE CYCLE)

1. A write occurs during the overlap(tWP) of a low /CS and low /WE. A write begins at the latest transition among

/CS going low and /WE going low : A write end at the earliest transition among /CS going high and /WE going

high, tWP is measured from the beginning of write to the end of write.

2. tCW is measured from the later of /CS going low to end of write.

3. tAS is measured from the address valid to the beginning of write.

4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS, or /WE

going high.