ELECTRONICS

KM62V256C, KM62U256C Family

CMOS SRAM

Revision 04

April 1996

- 6 -

KM62V256CL-L

KM62U256CL-L

KM62V256CLE-L

KM62U256CLE-L

KM62V256CLI-L

KM62U256CLI-L

Vcc

3.0/2.7V*

2.2V

/CS

GND

/CS¡ Ã

Vcc-0.2V

Vdr

tSDR

tRDR

Data retention mode

DATA RETENTION TIMING DIAGRAM

Vcc for data retention

Data retention current

Data retention set-up time

Recovery time

DATA RETENTION CHARACTERISTICS

Vdr

Idr

tSDR

tRDR

Vcc=3.0V

See data retention

waveform

Typ**

-

1

0.6

1

0.6

1

0.6

-

-

Unit

V

uA

ms

Min

2.0

-

-

-

-

-

-

0

5

Max

3.6

8

8

10

10

10

10

-

-

* 1) Commercial Product : Ta=0 to 70 °C, unless otherwise specified

2) Extended Product : Ta=-25 to 85 °C, unless otherwise specified

3) Industrial Product : Ta=-40 to 85 °C, unless otherwise specified

** Ta=25 °C

Item

Symbol

Test Condition*

* 3.0V for KM62V256C family, 2.7V for KM62U256C family

FUNCTIONAL DESCRIPTION

/WE

X

H

H

L

Mode

Power Down

Output Disable

Read

Write

Current Mode

Isb, Isb1

Icc

Icc

Icc

I/O Pin

High-Z

High-Z

Dout

Din

/OE

X

H

L

X

/CS

H

L

L

L