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1.1.MII Signal Description
Pin#
Signal
I/O
Description
55
TXC
I
Transmit Clock
This pin provides a continuous clock as a timing reference for TXD[3:0] and
TXEN. TXC is sourced by the PHY. TXC is 2.5 MHz in 10BASET Nibble
mode, and 25 MHz in 100BASETX Nibble mode.
53
TXEN
O
Transmit Enable
This output signal indicates the presence of a valid nibble data on TXD[3:0]. It
becomes active when the first nibble data of the packet is valid on TXD[3:0]
and goes low after the last nibble data of the packet is clocked out of
TXD[3:0]. This signal connects directly to the PHY device. This signal is active
high.
52
51
50
49
TXD[3]
TXD[2]
TXD[1]
TXD[0]
O
Transmit Data
These pins provide Nibble NRZ data to the PHY synchronously with TXC
when TXEN is asserted.
46
RXC
I
Receive Clock
This pin provides a continuous clock reference for RXDV and RXD[3:0]
signals. RXC is sourced by the PHY. RXC is 2.5 MHz in 10BASET Nibble
mode, and 25 MHz in 100BASETX Nibble mode.
48
COL
I
Collision Detect
This pin becomes active when a collision has been detected in Half Duplex
modes. This signal is asynchronous, active high and ignored during full-
duplex operation. This signal is active high.
47
CRS
I
Carrier Sense
This pin indicates that carrier is present. This signal is active high.
44
RXDV
I
Receive Data Valid
This signal is asserted high when received data is present on the RXD[3:0]
pins; the signal is deasserted at the end of the packet. The signal is valid on
the rising of the RXC.
43
42
41
40
RXD[3]
RXD[2]
RXD[1]
RXD[0]
I
Receive Data
These pins receive Nibble NRZ data from the PHY device synchronously with
RXC when RXDV is asserted.
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