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MTD516 Revision 1.2 19/06/2000
MTD516
(Preliminary)
MYSON
TECHNOLOGY
2.0 PIN DESCRIPTIONS
RMII Port Interface Pins
Name
Pin Number
I/O
Descriptions
CRSDV0
186
I
Port0 RMII receive interface signal, CRSDV0 is asserted high when
port0 media is non_idle.
RXD0_0
RXD0_1
187
188
I
I
Port0 RMII receive data bit_0.
Port0 RMII receive data bit_1.
TXEN0
185
O
Port0 RMII transmit enable signal.
TXD0_0
TXD0_1
184
183
O
O
Port0 RMII transmit data bit_0.
Port0 RMII transmit data bit_1.
CRSDV1
194
I
Port1 RMII receive interface signal, CRSDV1 is asserted high when
port1 media is non_idle.
RXD1_0
RXD1_1
195
196
I
I
Port1 RMII receive data bit_0.
Port1 RMII receive data bit_1.
TXEN1
193
O
Port1 RMII transmit enable signal.
TXD1_0
TXD1_1
192
191
O
O
Port1 RMII transmit data bit_0.
Port1 RMII transmit data bit_1.
CRSDV2
200
I
Port2 RMII receive interface signal, CRSDV2 is asserted high when
port2 media is non_idle.
RXD2_0
RXD2_1
201
202
I
I
Port2 RMII receive data bit_0.
Port2 RMII receive data bit_1.
TXEN2
199
O
Port2 RMII transmit enable signal.
TXD2_0
TXD2_1
198
197
O
O
Port2 RMII transmit data bit_0.
Port2 RMII transmit data bit_1.
CRSDV3
206
I
Port3 RMII receive interface signal, CRSDV0 is asserted high when
port3 media is non_idle.
RXD3_0
RXD3_1
207
208
I
I
Port3 RMII receive data bit_0.
Port3 RMII receive data bit_1.
TXEN3
205
O
Port3 RMII transmit enable signal.
TXD3_0
TXD3_1
204
203
O
O
Port3 RMII transmit data bit_0.
Port3 RMII transmit data bit_1.
CRSDV4
4
I
Port4 RMII/MII receive interface signal, CRSDV4 is asserted high when
port4 media is non_idle.
RXD4_0
RXD4_1
5
6
I
I
Port4 RMII/MII receive data bit_0.
Port4 RMII/MII receive data bit_1.
TXEN4
3
O
Port4 RMII transmit enable signal
TXD4_0
TXD4_1
2
1
O
O
Port4 RMII/MII transmit data bit_0.
Port4 RMII/MII transmit data bit_1.
CRSDV5
12
I
Port5 RMII receive interface signal, CRSDV5 is asserted high when
port5 media is non_idle.
RXD5_0
RXD5_1
13
14
I
I
Port5 RMII receive data bit_0.
Port5 RMII receive data bit_1.
TXEN5
9
O
Port5 RMII transmit enable signal.
TXD5_0
TXD5_1
8
7
O
O
Port5 RMII transmit data bit_0.
Port5 RMII transmit data bit_1.
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