CY28435 datasheet(1/23 Pages) CYPRESS

Part #	CY28435

Description	Clock Generator for Intel Grantsdale Chipset

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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PRELIMINARY

Clock Generator for Intel Grantsdale Chipset

CY28435

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

, CA 95134

•

408-943-2600

Document #: 38-07664 Rev. *B

Revised December 21, 2004

Features

• Compliant to Intel CK410

• Supports Intel Prescott and Tejas CPU

• Selectable CPU frequencies

• Differential CPU clock pairs

• 100-MHz differential SRC clocks

• 96-MHz differential dot clock

• 48-MHz USB clocks

• 33-MHz PCI clock

• Dynamic Frequency Control

• Dial-A-Frequency

•Watchdog

• Two Independent Overclocking PLLs

• Low-voltage frequency select input

•I2C support with readback capabilities

• Ideal Lexmark Spread Spectrum profile for maximum

electromagnetic interference (EMI) reduction

• 3.3V power supply

• 56-pin SSOP and TSSOP packages

CPU

SRC

PCI

REF

DOT96

USB

x 2

x 7

x 9

x 2

x 1

x 2

Block Diagram

Pin Configuration

VDD_RE

F

VDD_CPU

VDD_SRC

VTTPWR_GD#/PD

PLL Reference

VDD_SRC

VDD_PCI

FS_[E:A]

SRC

PLL

CPU

PLL

VDD_48Mhz

VDD_48

SDATA

PLL

Divider

FIX

PLL

Divider

VDD_SRC

VDD_CPU

IREF

RE

F

CPUT

CPUC

SRCT

SRCC

SRCT4_SATA

SRCC4_SATA

DOT96T

DOT96C

USB

PCI

Watchdog

Timer

SRESET#

I2C

Logic

SDATA

SCLK

14.318MHz

Crystal

Xin

Xout

VDD_PCI

PCIF

ITP_EN

Dynamic

Frequency

DF[2:0]

DF_EN

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

1

2

3

4

5

6

7

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

VSS_PCI

VDD_PCI

DF2/PCI3

*FS_E/PCI4

PCI5

VSS_PCI

VDD_PCI

**SRESET_EN/PCIF1

**DF_EN/PCIF0

VDD_48

USB48_0

VSS_48

DOT96T

DOT96C

*FS_B/USB48_1

**VTTPWRGD#/PD

**FS_A

SRCT1

SRCC1

VDD_SRC

SRCT2

SRCC2

SRCT3

SRCC3

SRCT4_SATA

SRCC4_SATA

VDD_SRC

PCIF2

PCI1/DF0

PCI2/DF1

PCI0/SRESET#

REF1/**FS_C

REF0/**FS_D

VSS_REF

XIN

VDD_REF

XOUT

SCLK

VSS_CPU

CPUT0

CPUC0

VDD_CPU

CPUT1

CPUC1

IREF

VSSA

VDDA

SRCT7

SRCC7

VDD_SRC

SRCT6

SRCC6

SRCT5

SRCC5

VSS_SRC

SDATA

* indicates internal pull-up

** indicates internal pull-down

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