6.42

IDT70V9389/289L

High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM

Industrial & Commercial Temperature Ranges

11

Timing Waveform of Read Cycle for

Timing Waveform of Read Cycle for Pipelined Operation

An

An + 1

An + 2

An + 3

ADDRESS

CLK

OE

Qn

Qn + 1

Qn + 2

4856 drw 06

(1)

(1)

(1)

(1)

(2)

UB, LB

(5)

..

An

An + 1

An + 2

An + 3

ADDRESS

CLK

UB, LB

(4)

OE

Qn

Qn + 1

Qn + 2

4856 drw 07

(1)

(1)

(1)

(2)

(5)

(1 Latency)

(6)

(6)

NOTES:

1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).

2. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.

are for reference use only.

7. "X' here denotes Left or Right port. The diagram is with respect to that port.