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Z16C3220VSC Datasheet(PDF) 8 Page - Zilog, Inc. |
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Z16C3220VSC Datasheet(HTML) 8 Page - Zilog, Inc. |
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8 / 121 page  8 PRELIMINARY Z16C32 IUSC™ PS97USC0200 ZILOG PIN DESCRIPTION (Continued) /BUSREQ Bus Request (output, active Low). The DMA controller section drives this line Low to request control of the host bus. /BUSREQ can be an open-drain or totem- pole output depending on a bit in the Bus Configuration Register. In open-drain mode the IUSC samples the pin as an input and only drives it Low after sampling it high. /BIN Bus Acknowledge In (input, active Low). When the IUSC receives a falling edge on this input, it samples whether it has been driving (or has just begun to drive) /BUSREQ. If so, it keeps /BOUT High and takes control of the host bus. If not, it passes the bus grant by driving /BOUT Low. This signal can be used with /BOUT to form a bus-grant daisy chain for arbitration of bus control. Alter- natively, it can be connected to a direct, positive grant from an external arbiter, and the /BOUT pin can be left uncon- nected. /BOUT Bus Acknowledge Out (output, active Low). As noted above, this signal can be used with /BIN to form a bus-grant daisy chain for arbitration of bus control. /ABORT Abort Master Cycle (input, active Low ). A Low on this line during a master cycle makes the currently active DMA channel terminate its activity and enter a disabled state. Note that /ABORT is only effective during a DMA cycle, so that the IUSC knows which channel should be aborted. Also note that external logic must set /WAIT//RDY to the right state for the cycle to complete, before /ABORT becomes effective. RxD Received Data (input, positive logic). The serial input. TxD Transmit Data (output, positive logic). The serial output. /RxC Receive Clock (input or output). This signal can be used as a clock input for any of the functional blocks in the serial controller. Or, software can program the IUSC so that this pin is an output carrying any of several receiver or internal clock signals, a general-purpose input or output, or an interrupt input. /TxC Transmit Clock (input or output). This signal can be used as a clock input for any of the functional blocks in the serial controller. Or, software can program the IUSC so that this pin is an output carrying any of several transmitter or internal clock signals, a general purpose input or output, or an interrupt input. /RxREQ Receive DMA Request (input or output). In device testing or in applications not using the serial controller and DMA controller sections together in the usual way, this pin can carry an active Low DMA Request from the receive FIFO. On the IUSC this request is internally routed to the on-chip Receive DMA channel; it is more typical to use the RxREQ pin as a general-purpose output or as an interrupt input. /TxREQ Transmit DMA Request (input or output). In device testing or in applications not using the serial controller and DMA controller sections together in the usual way, this pin can carry an active Low DMA Request from the transmit FIFO. On the IUSC this request is internally routed to the on-chip Transmit DMA channel, and it’s more typical to use the RxREQ pin as a general-purpose output or as an interrupt input. /DCD Data Carrier Detect (input or output, active Low). Software can program the IUSC so that this signal enables/ disables the receiver. In addition, software can program the device to request interrupts in response to transitions on this line. The pin can also be used as a simple input or output. /CTS Clear to Send (input or output, active Low). Software can program the IUSC so that this signal enables/disables the transmitter. In addition, software can program the device to request interrupts in response to transitions on this line. The pin can also be used as a simple input or output. |
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