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Z8922320FSC Datasheet(PDF) 2 Page - Zilog, Inc.

Part # Z8922320FSC
Description  16-BIT DIGITAL SIGNAL PROCESSORS WITH A/D CONVERTER
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Manufacturer  ZILOG [Zilog, Inc.]
Direct Link  http://www.zilog.com
Logo ZILOG - Zilog, Inc.

Z8922320FSC Datasheet(HTML) 2 Page - Zilog, Inc.

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Z89223/273/323/373
16-Bit Digital Signal Processors with A/D Converter
ZiLOG
2
DS000202-DSP0599
GENERAL DESCRIPTION (Continued)
OTP version of the Z89223/323, is ideal for prototypes and
early production builds.
Throughout this specification, references to the Z893x3 de-
vice apply equally to the Z89223/273/323/373, unless oth-
erwise specified.
Notes: All signals with an overline are active Low. For
example, in RD/WR, RD is active High and WR is
active Low. For I/O ports, P1.3 denotes Port1 bit 3. Pins
called NC are “No Connection”—they do not connect
any power, grounds, or signals.
Power connections follow conventional descriptions:
Connection
Circuit
Device
Power
VCC
VDD
Ground
GND
VSS
Figure 1. Z892X3/3x3 Functional Block Diagram
Data RAM1
256x16
Shifter
XY
Multiplier
P
P2:1
P1:1
P0:1
DDATA
8
8
816
16
16
16
16
16
16
16
24
16 MSB
16 MSB
24
16
16
24
24
24
16 MSB
D0:1–3:1
Addr
Gen
Unit1
8-Bit
A/D
AN0
VAHI
EA2–EA0
ED15–ED0
DS
WAIT
RD/WR
Port 0
Port 1
Port 2
AN1
AN2
AN3
VALO
P1.1 or CLKOUT
P1.0 or INT2
P1.2 or SDI
P1.3 or SDO
P1.4 or SS
P1.5 or SCLK
P1.6 or UI0
P1.7 or UI1
8-Bit I/O
8-Bit I/O
16-Bit Counter
Timer
16-Bit Counter
Timer, PWM
16-Bit Counter
Timer, PWM
SPI
4 Inputs
4 Outputs
P2.1 or INT1
P2.0 or INT0
P2.2 or TMO0
P2.3 or TMO1
P2.4 or WAIT
P2.5 or UI2
P2.6 or TMO2
P2.7
P3.7–P3.4
P3.3–P3.0
16-Bit
Peripheral
Interface
Data RAM0
256x16
Program
ROM/OTP
8192x16
P2:0
P1:0
P0:0
8
D0:0–3:0
Addr
Gen
Unit0
Program
Control
Unit
Phase
Locked
Loop
Bank
Switch
Stack
MUX
ALU
Accumulator
HALT
RESET
CLKI
CLKO
V
AGND
LPF
DD
VSS
AVCC
24


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