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Z8523016PEC Datasheet(PDF) 5 Page - Zilog, Inc.

Part # Z8523016PEC
Description  ENHANCED SERIAL COMMUNICATIONS CONTROLLER
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Manufacturer  ZILOG [Zilog, Inc.]
Direct Link  http://www.zilog.com
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Z8523016PEC Datasheet(HTML) 5 Page - Zilog, Inc.

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List of Figures
Figure 1.
Z85230 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Figure 2.
Z80230 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Figure 3.
Z85230 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 4.
Z80230 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 5.
ESCC Transmit Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 6.
ESCC Receive Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 7.
ESCC Interrupt Priority Schedule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 8.
Various ESCC Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 9.
Detecting 5- or 7-Bit Synchronous Characters . . . . . . . . . . . . . . . . . . . . . . 17
Figure 10. SDLC Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 11. Data Encoding Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 12. Write Register 7 Prime (WR7’) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 13. DMA Request on Transmit Deactivation Timing . . . . . . . . . . . . . . . . . . . . 25
Figure 14. TxIP Latching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 15. DPLL Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 16. SDLC Frame Status FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 17. SDLC Byte Counting Detail 32
Figure 18. Z80230 Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 19. Z80230 Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 20. Z80230 Interrupt Acknowledge Cycle Timing . . . . . . . . . . . . . . . . . . . . . . 74
Figure 21. Read Cycle Timing (Z85230) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 22. Write Cycle Timing (Z85230) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 23. Interrupt Acknowledge Cycle Timing (Z85230) . . . . . . . . . . . . . . . . . . . . . 76
Figure 24. Standard and Open-Drain Test Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 25. Z80230 Read/Write Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 26. Z80230 Interrupt Acknowledge Timing Diagram . . . . . . . . . . . . . . . . . . . . 81
Figure 27. Z80230 Reset Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 28. Z80230 General Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 29. Z85230 Read/Write Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 30. Z85230 Reset Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 31. Z85230 Interrupt Acknowledge Timing Diagram . . . . . . . . . . . . . . . . . . . . 92
Figure 32. Z85230 Cycle Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 33. Z85230 System Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100


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