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IDT72V36102L10PF Datasheet(PDF) 8 Page - Integrated Device Technology |
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IDT72V36102L10PF Datasheet(HTML) 8 Page - Integrated Device Technology |
8 / 29 page 8 COMMERCIALTEMPERATURERANGE IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFOTM 16,384 x 36 x 2, 32,768 x 36 x 2 and 65,536 x 36 x 2 IDT72V3682L10 IDT72V3682L15 IDT72V3692L10 IDT72V3692L15 IDT72V36102L10 IDT72V36102L15 Symbol Parameter Min. Max. Min. Max. Unit fS Clock Frequency, CLKA or CLKB — 100 — 66.7 MHz tCLK Clock Cycle Time, CLKA or CLKB 10 — 15 — ns tCLKH Pulse Duration, CLKA or CLKB HIGH 4.5 — 6 — ns tCLKL Pulse Duration, CLKA and CLKB LOW 4.5 — 6 — ns tDS Setup Time, A0-A35 before CLKA ↑ and B0-B35 3 — 4 — ns before CLKB ↑ tENS1 Setup Time, CSA and W/RA, before 4 — 4.5 — ns CLKA ↑; CSB, and W/RB before CLKB↑ tENS2 Setup Time, ENA and MBA, before 3 — 4.5 — ns CLKA ↑; ENB, and MBB before CLKB↑ tRSTS Setup Time, RST1 or RST2 LOW before CLKA ↑ 5— 5— ns or CLKB ↑(1) tFSS Setup Time, FS0 and FS1 before RST1 and RST2 HIGH 7.5 — 7.5 — ns tFWS Setup Time, FWFT before CLKA ↑ 0— 0— ns tDH Hold Time, A0-A35 after CLKA ↑ and B0-B35 after CLKB↑ 0.5 — 1 — ns tENH Hold Time, CSA, W/RA, ENA, and MBA after CLKA ↑; 0.5 — 1 — ns CSB, W/RB, ENB, and MBB after CLKB ↑ tRSTH Hold Time, RST1 or RST2 LOW after CLKA ↑ or CLKB↑(1) 4— 4— ns tFSH Hold Time, FS0 and FS1 after RST1 and RST2 HIGH 2 — 2 — ns tSKEW1(2) Skew Time, between CLKA ↑ and CLKB↑ for EFA/ORA, 7.5 — 7.5 — ns EFB/ORB, FFA/IRA, and FFB/IRB tSKEW2(2,3) Skew Time, between CLKA ↑ and CLKB↑ for AEA,12 — 12 — ns AEB, AFA, and AFB NOTES: 1. Requirement to count the clock edge as one of at least four needed to reset a FIFO. 2. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle. 3. Design simulated, not tested. TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE (Vcc = 3.3V ± 0.15V; TA = 0ο C to +70ο C; JEDEC JESD8-A compliant) |
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