RTI-3
1.0 ARCHITECTURE AND OPERATION
The UT1553B RTI is an interface device linking a MIL-
STD-1553 serial data bus and a host microprocessor system.
The RTI’s MIL-STD-1553B interface includes encoding/
decoding logic, error detection, command recognition,
memory address control, clock, and reset circuits.
Decoders
The UT1553B RTI contains two separate free-running
decoders to insure that all redundancy requirements of MIL-
STD-1553B are met. Each decoder receives, decodes, and
verifies biphase Manchester II data. Proper frequency and
edge skew are also verified.
Command Recognition Logic
The command recognition logic monitors the output of both
decoders at all times. Recognition of a valid command
causes a reset of present interface activity followed by
execution of the command. This procedure meets the
requirement for superseding valid commands.
Encoder
The encoder receives serial data from the data transfer logic,
converts it to Manchester II form with proper
synchronization and parity, and passes it to the output and
self-test logic.
Data Transfer Logic
The data transfer logic provides double-buffered 16-bit
parallel-to-serial and serial-to-parallel conversion during
reception and transmission of data.
Memory Address Control
The memory address control logic controls the output of the
three-state address lines during memory access. In DMA
system implementations, the memory address control
provides RTI-generated addresses. In a pseudo-dual-port
memory configuration, the memory address control logic
provides either RTI-generated or host system addressing.
Control and Error Logic
The control and error logic performs the following four
major functions:
-
Interface control for proper processing of MIL-
STD-1553B commands
-
Error checking of both MIL-STD-1553B data and
RTI operation
-
Memory control (DMA or pseudo-dual-port) for
proper data transfer
-
Operational status and control signal generation
Output Multiplexing and Self-Test Logic
This logic directs the output of the encoder to one of four
places:- Channel A outputs
- Channel B outputs
- Channel A decoders during self-test
- Channel B decoders during self-test
Clock and Reset Logic
The UT1553B RTI requires a 12MHz input clock to operate
properly. The RTI provides a 2MHz output for the system
designer to use. The device provides a hardware reset pin
as well as software-generated reset.
Timer Logic
The UT1553B RTI has a built-in 730ms timer that is
activated when the encoder is about to transmit. The timer
is reset upon receipt of a valid command, master reset, or a
time-out condition.
1.1 HOST INTERFACE
Configure the RTI into the host system for either a direct
memory or transparent memory access. The following
sections discuss the system configuration for each method
of memory management.
1.1.1 Direct Memory Access
In the direct memory access configuration the RTI and host
arbitrate for the shared 2K x 16 memory space. To request
access to memory the RTI asserts direct memory request
output (DMARQ); the system bus arbiter grants the RTI
access to memory by asserting the direct memory access
grant signal (MEMCK). The system arbiter should not assert
the MEMCK signal before the RTI has requested access to
memory (i.e., DMARQ asserted).
Once granted access to memory, the RTI address out
(ADDR OUT(10:0)), RAM chip select (RCS), RAM read/
write (RRD/RWR), and Data bus (DATA I/O(15:0)) provide
the interface signals to control the memory access. Figure
2 shows an example of a direct memory access system
configuration; for clarity the interface buffers and logic are
excluded. The host microprocessor also gains access to
memory by arbitration.
Take care to insure that bus contention does not occur
between the host and RTI Address buses or memory control
signals. To place the RTI Address Out bus in a high
impedance state negate the ADOEN input pin. Also note
that outputs RCS and RRD/RWR are not three-state outputs.
When the RTI is not writing to memory, bidirectional Data
bus DATA I/O(15:0) is an input (i.e., not actively driving
the bus).
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