9

T6819/T6829 [Preliminary]

4531B–BCD–11/03

3.5

Thermal shutdown on

T

j switch on

135

160

185

°CB

3.6

Thermal shutdown

hysteresis

DT

j switch off

15

K

B

3.7

Ratio thermal shutdown

off/thermal prewarning

set

T

jPW set

1.05

1.2

B

3.8

Ratio thermal shutdown

on/thermal prewarning

reset

T

j switch on/

1.05

1.2

B

4

Output Specification (OUT1-OUT3)

4.1

On resistance

I

4, 13,

14

R

DS On 1-3 H

1.1

W

A

4.2

I

2, 3, 15

R

DS On 1-3 L

1.1

W

A

4.3

High-side output

leakage current

V

output stages off

4, 13,

14

I

Out 1-3 H

-5

µA

A

4.4

Low-side output

leakage current

V

output stages off

2, 3, 15

5

µA

A

4.5

High-side switch

reverse diode forward

voltage

I

4, 13,

14

V

1.5

V

A

4.6

Low-side switch reverse

diode forward voltage

I

2, 3, 15

V

Out 1-3 L

-1.5

V

A

4.7

High-side overcurrent

limitation and shutdown

threshold

4, 13,

14

-2.5

-2

-1.5

A

A

4.8

Low-side overcurrent

limitation and shutdown

threshold

2, 3, 15

I

Out 1-3 L

1.5

2

2.5

A

A

4.9

Overcurrent shutdown

delay time

t

dSd

10

40

µs

A

4.10

High-side open load

detection current

Input register bit 13

(OLD) = low, output off

4, 13,

14

I

Out 1-3 H

-2.5

-0.2

mA

A

4.11

Low-side open load

detection current

Input register bit 13

(OLD) = low, output off

2, 3, 15

0.2

2.5

mA

A

4.12

High-side output switch

on delay

(1),(2)

R

t

don

20

µs

A

4.13

Low-side output switch

on delay

(1),(2)

V

R

t

don

20

µs

A

4.14

High-side output switch

off delay

(1),(2)

V

20

µs

A

Electrical Characteristics (Continued)

7.5 V < V

No.

Parameters

Test Conditions

Pin

Symbol

Min.

Typ.

Max.

Unit

Type*

*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

Note:

1. Delay time between rising edge of input signal at pin CS after data transmission and switch on/off output stages to 90% of

final level. Device not in standby for t > 1 ms.

2. Delay time between rising/falling edge of input signal at pin PWM and switch on/off output stages to 90% of final level.

3. Difference between switch-on and switch-off delay time of input signal at pin PWM to output stages in PWM mode.