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ADC088S022CIMT Datasheet(PDF) 2 Page - National Semiconductor (TI) |
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ADC088S022CIMT Datasheet(HTML) 2 Page - National Semiconductor (TI) |
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2 / 17 page  Block Diagram 20166707 Pin Descriptions Pin No. Symbol Description ANALOG I/O 4 - 11 IN0 to IN7 Analog inputs. These signals can range from 0V to V REF. DIGITAL I/O 16 SCLK Digital clock input. The guaranteed performance range of frequencies for this input is 8 MHz to 16 MHz. This clock directly controls the conversion and readout processes. 15 DOUT Digital data output. The output samples are clocked out of this pin on the falling edges of the SCLK pin. 14 DIN Digital data input. The ADC088S022’s Control Register is loaded through this pin on rising edges of the SCLK pin. 1CS Chip select. On the falling edge of CS, a conversion process begins. Conversions continue as long as CS is held low. POWER SUPPLY 2V A Positive analog supply pin. This voltage is also used as the reference voltage. This pin should be connected to a quiet +2.7V to +5.25V source and bypassed to GND with 1 µF and 0.1 µF monolithic ceramic capacitors located within 1 cm of the power pin. 13 V D Positive digital supply pin. This pin should be connected to a +2.7V to V A supply, and bypassed to GND with a 0.1 µF monolithic ceramic capacitor located within 1 cm of the power pin. 3 AGND The ground return for the analog supply and signals. 12 DGND The ground return for the digital supply and signals. www.national.com 2 |
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