Semiconductor

MSC23140D

Notes: 1. A start-up delay of 200µs is required after power-up, followed by a minimum of eight initialization cycles

(/RAS only refresh or /CAS before /RAS refresh) before proper device operation is achieved.

4. This parameter is measured with a load circuit equivalent to 2TTL loads and 100pF.

not referenced to output voltage levels.

≥ t

≥ t

≥ t

≥ t

≥ t

data read from the selected cell; if neither or the above sets of conditions is satisfied, the conditions of

the data out (at access time) is indeterminate.

10. These parameters are referenced to /CAS leading edge in an early write cycle, and to /WE leading edge

in an /OE control write cycle or a read modify write cycle.

11. The test mode is initiated by performing a /WE and /CAS before /RAS refresh cycle. This mode is

latched and remains in effect until the exit cycle is generated. The test mode specified in this data sheet

is a 2-bit parallel test function. CA0 is not used. In a read cycle, if all internal bits are equal, the DQ pin

will indicate a high level. If any internal bits are not equal, the DQ pin will indicate a low level.

The test mode is cleared and the memory device returned to its normal operating state by a /RAS only

refresh or /CAS before /RAS refresh cycle.

12. In a test mode read cycle, the value of access time parameters is delayed for 5ns for the specified value.

These parameters should be specified in test mode cycle by adding the above value to the specified

value in this data sheet.