INF8582E

4

- bus is free (not engaged) - both lines are in "high" mode;

- transmission start (condition "Start") - passing of the line SDA from "high" level to

"low" when SCL is in "high" mode;

- data transmission;

- end of transmission (condition "Stop") - passing of the line SDA from "low" level to

"high" while the line SCL is in "high" mode.

The data transmission can start only when the bus is free. During the data transmission

the data line must be stable all the time while clock line is “high”. The SDA line mode can

change only when the clock signals line SCL is in “low” mode. One clock signal falls at one data

bit. The change in SDA line mode when Clock line is “high” will be interpreted as check signals:

“Start” or “Stop”.

Each transmission of data starts with the condition “Start” and is finished with the condition

“Stop”. The information is always transmitted in bytes. The number of data bytes transmitted be-

tween the conditions “Start” and “Stop” is limited in “Erasure/recording” mode and not limited in

edgment bit. This bit is always generated on SDA line by the device which received the previous

data byte (i.e. “receiver”). The device acknowledging the receipt of the data (if it meets the re-

quirements), rarefies the SDA line so that this line is constantly “low” during all period of “high”

ing acknowledgment forming must take the mode with high output resistance. If the received

data byte does not comply with the requirements, the receiving device does not generate the

control the data transmission along the bus (microcontrollers, microprocessors), and «subordi-

nate» devices, which are controlled by «main» devices (service and peripheric devices). In their

turn the both groupsof devices may be as «receivers» (devices receiving the data at that mo-

ment) and «transmitters» (devices transmitting the data the bus). The designed microcircuit

INF8582E may be only «subordinate receiver» or «subordinate transmitter».The time diagram of

Fig. 3

SDA

SCL

SDA

1

8

9