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¡ Semiconductor

MSM6981-01

PIN DESCRIPTION

Symbol

Description

Pin

PD0 to PD15

1 to 10

36 to 41

SID

11

SICK

12

ISYNC

13

MCK

14

PBS

15

RST

16

DATD

17

POWD

18

WDT

19

EXTI

20

GND

21

CKOUT

22

IS/P

23

CKRST

24

C/D

25

Bidirectional bus interface.

PD15 is the MSB pin.

Refer to Tables 1 and 2 for the specifications and Figures 1 and 3 for the timings.

When RST or OSYNC is a logic "0", all of outputs PD0 to PD15 are "1"s with an

impedance of 100 k

W or more. A logic "0" means low level input/output voltage

and a logic "1" high level input/output voltage.

Serial data input. The bit length is 4 or 8.

Refer to Fig.2.

Clock signal input for serial input data.

The maximum clock rate is 2048 kbps. The input clock count should be longer

than the serial data bit length. Refter to Fig.2.

Synchronous pulse signal input.

For taking in the serial or parallel data.

Main clock input. 20 MHz clock input.

Chip test input.

Input a logic "0" to this pin.

Reset signal input.

Input a logic "0" while the main clock (MCK) is input. Provide the timing indicated

in Fig.6 to make the first output data effective.

While a logic "0" is input to RST, PD0 to PD15 output a logic "1" with a high output

impedance of 100 k

W or more, and SOD is in a high impedance state.

Chip test output.

Chip test output.

Chip test output.

Also available for the internal observation signal.

When the device is operating normally, the signal synchronized with ISYNC is

output from WDT. Refter to Fig.5.

Chip test input.

Normally input a logic "1" to this pin.

Ground. 0 V.

Chip test output.

Normally 1/4 main clock (MCK) frequency is output (5 MHz).

Serial/Parallel data input select signal.

Logic "1": Serial data input.

Logic "0": Parallel data input.

Refer to Table 1.

Chip test input.

Normally pull this pin to a logic "1".

Operating mode select input.

Logic "1": Coding mode.

Logic "0": Decoding mode.

Refer to Table 1.