PEDR27V6466F-01-08

1Semiconductor

MR27V6466F

10/39

READ OPERATIONS

Clock (CLK)

The clock input enables MR27V6466F to sample all the inputs, to control internal circuitry, and to turn on output

drivers. All timings are referred to the rising edge of the clock. All inputs with high level CKE and low level

CS

should be valid at the rising edge of CLK for proper functionality.

Clock Enable (CKE)

The clock enable (CKE) turns on or switches off the admission of the clock input into the internal clock signal lines.

All internal circuits are controlled by the internal clock signal to implement each command. High level CKE

sampled at CKE

CKE

The

suspension of internal clock signal in all state ignores new input except CKE, and holds internal state and output

state. Low level CKE in Active Standby state, defined as Power Down state, cuts power dissipation. In Power

Down state, the contents of mode resister and Row Address are preserved. After recovering high level CKE to exit

from Power Down state, MR27V6466F is in Active Standby state. Low level CKE just after the sampling of

"Read" command till the completion of burst read, defined as Clock Suspend, makes read operation go on with

power dissipation. Any command operation does not interrupted by arbitrary low level CKE. Sampling command

with low level CKE preceded with high level CKE is illegal.

Power On

Apply power and start clock considering following issues.

1.

During power on, Mode Register is initialized into the default state.

(default state: CAS latency = 5, Burst Type = Sequential, Burst length = 4)

2.

After power on, MR27V6466F is in Active Standby state and ready for "Mode Register set" command or

"Row Active" command. MR27V6466F requires neither command nor waiting time as power on sequence

after starting CLK input in order to start "Row Active" command to read data.

3.

It is recommended in order to utilize default state of Mode Register that

MR and CKE inputs are maintained

to be pulled up during power on till the implementation of the first "Row Active" command. After above

power on, "Row Active" command and "Read" command can be started immediately on default Mode

Register state.

4.

It is recommended that DQM input is maintained to be pulled up to prevent unexpected operation of output

buffers.

Organization Control

The organization of data output (DQ0~DQ31) depends on the logical level on WORD at the input timing of each

"Read" command. High level sampling of WORD derives double word mode (x32) output and low level sampling

of WORD derives word mode (x16) output. Constant WORD level input brings consistent organization.

MODE Register

Mode register stores the operating mode of MR27V6466F. Operating modes are consisted with CAS latency,

Burst Type and Burst Length. Registration of RAS latency is not required, because RAS to CAS delay (tRCD) is

requested independently of system clock. When the contents of Mode register are required to be changed for the

next operation, "Mode Register Set" command can be sampled at any cycle in Active Standby state. After "Mode

Register Set" command is sampled,

CS must be fixed to logical high level to prevent sampling of new command

input during succeeding three clock cycles.

Refer to Mode Resister Field Table for the relation between Operation modes and input pin assignment