FEDS8104166A-01

1Semiconductor

MS8104166A

10/19

OPERATION MODE

Write Operation Cycle

The write operation is controlled by seven control signals, SWCK1, SWCK2, RSTW1, RSTW2, WE1, WE2 and

IE1, IE2. Port1 write operation is accomplished by cycling SWCK1, and holding WE1 and IE1 high after the write

address pointer reset operation or RSTW1. RSTW1 must be preformed for internal circuit initialization before

Write operation.

Each write operation, which begins after RSTW1, must contain at least 140 active write cycles, i.e. SWCK1 cycles

while WE1 and IE1 are high. To transfer the last data to the DRAM array, which at that time is stored in the serial

data registers attached to the DRAM array, an RSTW1 operation is required after the last SWCK1 cycle.

Note that every write timing of MS8104166A is delayed by one clock compared with read timings for easy

cascading without any interface delay devices.

signals are input.

WE1, and IE1 control signals are input.

These operation are the same for Port1 and Port2.

Settings of WE1, 2 and IE1, 2 to the operation mode of Write address pointer and Data input.

WE1, 2

IE1, 2

Internal Write address pointer

Data input

H

H

Input

H

L

Incremented

L

X

Halted

Not input

X indicates “don’t care”

Read Operation Cycle

The read operation is controlled by seven control signals, SRCK, RSTR1, RSTR2, RE1, RE2, and OE1, OE2.

Port1 read operation is accomplished by cycling SRCK, and holding RE1 and OE1 high after the read address

pointer reset operation or RSTR1.

Each read operation, which begins after RSTR1, must contain at least 140 active read cycles, i.e. SRCK cycles

while RE1 and OE1 are high.

These operations are the same for Port1 and Port2.

Settings of RE1, 2 and OE1, 2 to the operation mode of read address pointer and Data output.

WE1, 2

IE1, 2

Internal Write address pointer

Data output

H

H

Output

H

L

Incremented

High impedance

L

X

Output

L

L

Halted

High impedance