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MSM9811 Datasheet(PDF) 4 Page - OKI electronic componets |
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MSM9811 Datasheet(HTML) 4 Page - OKI electronic componets |
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4 / 44 page  FEDL9811FULL-04 OKI Semiconductor MSM9811 4/44 PIN DESCRIPTIONS Pin Symbol Type Description 40-47, 49-64 RA23-RA0 O Address pins for external memory. These pins become high impedance when RCS pin is “H“. 30, 31, 33-38 RD7-RD0 I Data pin for external memory. Pull-down resistors are internally connected to these pins. These pull-down resistors become valid when the RCS pin is “H”, and become invalid when the RCS pin is “L”. 39 ROE O Output enable pin for external memory. This pin becomes high impedance when RCS pin is “H”. 8 RCS I When this pin is “L”, RA23 to RA0 and ROE pins output address data and output enable signal. When this pin is “H”, RA23 to RA0 and ROE pins become high impedance. 15 CMD I Select pin for Command data or Subcommand data for CPU interface. When this pin is “H”, subcommand input is selected. When this pin is “L”, command input is selected. A pull-up resistor is internally connected to this pin. 16 RD I Read pin for CPU interface. A pull-up resistor is internally connected to this pin. 18 WR I Write pin for CPU interface. A pull-up resistor is internally connected to this pin. 20 CS I Chip select pin for CPU interface. When CS is “H”, WR signal is not entered in this LSI. A pull-up resistor is internally connected to this pin. 14 SERIAL I CPU input interface select pin. When SERIAL is “H”, serial input interface is selected. When it is “L”, parallel input interface is selected. 28 D7/SD I/O Data bus pin for CPU interface when parallel input interface is selected. When WR is “L”, this pin serves as data input pin. When RD is “L”, this pin serves as channel status data output pin. When serial input interface is selected, this pin serves as serial data input pin. 27 D6/SI I/O Data bus pin for CPU interface when parallel input interface is selected. When WR is “L”, this pin serves as data input pin. When RD is “L”, this pin serves as channel status output pin. When serial input interface is selected, this pin serves as serial clock input pin. 26 D5/SO I/O Data bus pin for CPU interface when parallel input interface is selected. When WR is “L”, this pin serves as data input pin. When RD is “L”, this pin serves as channel status output pin. When serial input interface is selected, this pin serves as channel status serial output pin. |
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