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¡ Semiconductor

MSM514102D/DL

Notes:

1. A start-up delay of 200

µs is required after power-up, followed by a minimum of

eight initialization cycles (RAS-only refresh or CS before RAS refresh) before proper

device operation is achieved.

4. This parameter is measured with a load circuit equivalent to 2 TTL loads and 100 pF.

is not referenced to output voltage levels.

the cycle is an early write cycle and the data out will remain open circuit (high

contain data read from the selected cell; if neither of the above sets of conditions is

satisfied, then the condition of the data out (at access time) is indeterminate.

11. These parameters are referenced to the CS leading edge in an early write cycle, and

to the WE leading edge in a read modify write cycle.

12. The test mode is initiated by performing a WE and CS before RAS refresh cycle. This

mode is latched and remains in effect until the exit cycle is generated.

The test mode specified in this data sheet is an 8-bit parallel test function. RA10,

CA10 and CA0 are not used. In a read cycle, if all internal bits are equal, the data

output pin will indicate a high level. If any internal bits are not equal, the data

output pin will indicate a low level.

The test mode is cleared and the memory device returned to its normal operating

state by performing a RAS-only refresh cycle or a CS before RAS refresh cycle.

13. In a test mode read cycle, the value of access time parameters is delayed for 5 ns for the

specified value. These parameters should be specified in test mode cycle by adding the

above value to the specified value in this data sheet.