¡ Semiconductor

MSM548512L

7/12

Notes:

1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause

permanent damage to the device.

2. All voltages are referenced to ground.

open.

4. An initial pause of 100

µs is required after power-up followed by more than 8

initial cycles before proper device operation is achieved.

condition and is not referenced to output voltage levels.

7. In write cycles, the input data is latched at the earlier rising point of either CE

or WE. Write operation is achieved when both CE and WE are low.

8. The I/O state remains at high impedance after CE goes low if the transition occurs

at the same time as or after the falling edge of WE.

9. Use WE or OE or both signals to disable the output before input data is applied

during a write cycle when the input is not the same.

10. Data input must be set to floating state before I/O becomes low impedance by

WE or OE or both.

12. 2048-cycle refresh must be applied within 15

µs after the end of self refreshing

to satisfy 2048 cycles/32 ms.