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ML7055LP Datasheet(PDF) 7 Page - OKI electronic componets |
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ML7055LP Datasheet(HTML) 7 Page - OKI electronic componets |
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7 / 30 page  FEDL7055-02 OKI Semiconductor ML7055 7/30 RF I/F Pin Placement Pin Name Direc- tion [*0] Internal Pull Up/ Down, Schmitt Initial Value ML7055 HB ML7055 LA ML7055 LP Description PLLLOCK I Pull down — — — B4 B6 B5 ML7050: — CX72303: — BCM2002X: 1MHz clock H — PLL_OFF O — L D6 B1 B1 ML7050: PLL loop control 0: Open loop 1: Closed loop CX72303: Diversity output BCM2002X: PA Power control PCM I/F Pin Placement Pin Name Direc- tion Internal Pull Up/ Down, Schmitt Initial Value ML7055 HB ML7055 LA ML7055 LP Description PCMOUT O — L G6 J3 J4 PCM data output PCMIN I Pull up — H4 J5 H5 PCM data input PCMSYNC I/O Pull down — F5 J4 K4 PCM sync signal (8 kHz), Initial setting: input (can be switched by an internal register) PCMCLK I/O Pull down — G5 K4 H4 PCM clock (64 kHz/128 kHz) Initial setting: input (can be switched by an internal register) Note: The PCM sync signal (8 kHz) must be guaranteed at the accuracy of ±50 ppm if the PCMSYNC pin is configured as an input. UART I/F Pin Placement Pin Name Direc- tion Internal Pull Up/ Down, Schmitt Initial Value ML7055 HB ML7055 LA ML7055 LP Description SOUT O — H E7 F1 F2 ACE transmit serial data SIN I Schmitt — D4 G1 G2 ACE receive serial data RTS O — — G2 J9 K9 ACE transmit data ready CTS I — H F3 K9 J9 ACE transmit ready |
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