AN77L09 datasheet(4/8 Pages) PANASONIC

Part #	AN77L09

Description	3-pin Low Power Loss Voltage Regulato (100mA Type)

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Manufacturer	PANASONIC [Panasonic Semiconductor]

Direct Link	http://www.panasonic.com/industrial/

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4 / 8 page

4

Voltage Regulators

AN77L00/AN77L00M Series

Output voltage

Input stability

Load stability

Bias current under no load

Bias current fluctuation under load

Bias current before regulation start

Ripple rejection ratio

Min. input/output voltage difference (1)

Min. input/output voltage difference (2)

Output noise voltage

Output voltage temperature coefficient

Tj=25˚C

VI=5.18 to 15.18V, Tj=25˚C

IO= 0 to 100mA, Tj=25˚C

IO= 0mA, Tj=25˚C

IO= 0 to 100mA, Tj=25˚C

VI= 4.05V, IO= 0mA, Tj=25˚C

VI=7.18 to 6.18V, f=120Hz

VI= 4.05V, IO=50mA, Tj=25˚C

VI= 4.05V, IO=100mA, Tj=25˚C

f=10Hz to 100kHz

Tj= –30 to+125˚C

4.32

58

4.5

3

10

0.9

3

1.5

68

0.12

0.23

85

0.3

4.68

60

1.5

5

0.25

0.43

Parameter

Symbol

Condition

min

typ

max

Unit

s Electrical Characteristics (Ta=25˚C)

• AN77L045/M (4.5V, 100mA Type)

Note 1) Under Tj=25˚C, each test duration can be set short (within 10ms) and the characteristic drift with temperature rise at

joints of the chip may be ignored.

Note 2) VI=5.5V, IO=50mA, CO=10

µF unless otherwise specified.

VO

REGIN

REGL

Ibias

∆I

bias

Irush

RR

VDIF (min) 1

VDIF (min) 2

Vno

∆V

O/Ta

V

mV

mA

dB

V

µV

mV/˚C

Output voltage

Input stability

Load stability

Bias current under no load

Bias current fluctuation under load

Bias current before regulation start

Ripple rejection ratio

Min. input/output voltage difference (1)

Min. input/output voltage difference (2)

Output noise voltage

Output voltage temperature coefficient

Tj=25˚C

VI=5.7 to 15.7V, Tj=25˚C

IO= 0 to 100mA, Tj=25˚C

IO= 0mA, Tj=25˚C

IO= 0 to 100mA, Tj=25˚C

VI= 4.5V, IO= 0mA, Tj=25˚C

VI= 5.7 to 7.7V, f=120Hz

VI= 4.5V, IO= 50mA, Tj=25˚C

VI= 4.5V, IO= 100mA, Tj=25˚C

f=10Hz to 100kHz

Tj= –30 to+125˚C

4.8

58

5

4

10

0.9

3

1.5

68

0.12

0.24

90

0.33

5.2

60

1.5

5

0.25

0.3

Parameter

Symbol

Condition

min

typ

max

Unit

• AN77L05/M (5V, 100mA Type)

Note 1) Under Tj=25˚C, each test duration can be set short (within 10ms) and the characteristic drift with temperature rise at

joints of the chip may be ignored.

Note 2) VI=6V, IO=50mA, CO=10

µF unless otherwise specified.

VO

REGIN

REGL

Ibias

∆I

bias

Irush

RR

VDIF (min) 1

VDIF (min) 2

Vno

∆V

O/Ta

V

mV

mA

dB

V

µV

mV/˚C

Output voltage

Input stability

Load stability

Bias current under no load

Bias current fluctuation under load

Bias current before regulation start

Ripple rejection ratio

Min. input/output voltage difference (1)

Min. input/output voltage difference (2)

Output noise voltage

Output voltage temperature coefficient

Tj=25˚C

VI= 6.74 to 16.74V, Tj=25˚C

IO= 0 to 100mA, Tj=25˚C

IO= 0mA, Tj=25˚C

IO= 0 to 100mA, Tj=25˚C

VI= 5.4V, IO= 0mA, Tj=25˚C

VI= 6.74 to 8.74V, f=120Hz

VI=5.4V, IO=50mA, Tj=25˚C

VI=5.4V, IO=100mA, Tj=25˚C

f=10Hz to 100kHz

Tj= –30 to+125˚C

5.76

56

6

4

11

0.9

3

1.5

66

0.12

0.25

105

0.4

6.24

60

1.5

5

0.25

0.46

Parameter

Symbol

Condition

min

typ

max

Unit

• AN77L06/M (6V, 100mA Type)

Note 1) Under Tj=25˚C, each test duration can be set short (within 10ms) and the characteristic drift with temperature rise at

joints of the chip may be ignored.

Note 2) VI=7V, IO=50mA, CO=10

µF unless otherwise specified.

VO

REGIN

REGL

Ibias

∆I

bias

Irush

RR

VDIF (min) 1

VDIF (min) 2

Vno

∆V

O/Ta

V

mV

mA

dB

V

µV

mV/˚C

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