1 / 6 page
MPEG Clock Generator with VCXO
CY241V08A-41
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
, CA 95134
•
408-943-2600
Document #: 38-07655 Rev. *A
Revised April 22, 2004
Features
• Integrated phase-locked loop (PLL)
• Low-jitter, high-accuracy outputs
• VCXO with analog adjust
• 3.3V operation
Benefits
• Highest-performance PLL tailored for multimedia applica-
tions
• Meets critical timing requirements in complex system
designs
• Application compatibility for a wide variety of designs
Frequency Table
Part Number
Outputs
Input Frequency Range
Output Frequencies
VCXO Control
Curve
Other Features
CY241V08A-41
1
27-MHz pullable crystal input
per Cypress specification
One copy of 27 MHz
One copy of 83.33 MHz
(non-pullable)
linear
Pinout-compatible with
MK3741
27 XIN
XOUT
OSC
VCXO
VDD
VSS
Block Diagram
8-pin SOIC
CY241V08A-41
1
2
3
4
XOUT
XIN
VCXO
XBUF/27 MHz
VSS
REF
83.33 MHz
5
6
7
8
VDD
Pin Configuration
OUTPUT
DIVIDER
PLL
83.33MHz
XBUF/27MHz
54 REF
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
