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SY101474-3 Datasheet(PDF) 1 Page - List of Unclassifed Manufacturers

Part # SY101474-3
Description  1K x 4 ECL RAM
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Manufacturer  ETC1 [List of Unclassifed Manufacturers]
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SY101474-3 Datasheet(HTML) 1 Page - List of Unclassifed Manufacturers

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SY10/100/101474-3
SY10/100/101474-4
SY10/100/101474-5
SY10/100/101474-7
DESCRIPTION
SYNERGY
SEMICONDUCTOR
FEATURES
s Address access time, tAA: 3/4/5/7ns max.
s Chip select access time, tAC: 2ns max.
s Write pulse width, tWW: 3ns min.
s Edge rate, tr/tf: 500ps typ.
s Power supply current, IEE: –300mA, –220mA
for –5/7ns
s Superior immunity against alpha particles provides
virtually no soft error sensitivity
s Built with advanced ASSET™ technology
s Fully compatible with industry standard 10K/100K
ECL I/O levels
s Noise margins improved with on-chip voltage and
temperature compensation
s Open emitter output for easy memory expansion
s ESD protection of 2000V
s Available in 24-pin Flatpack and 28-pin PLCC and
MLCC packages
The Synergy SY10/100/101474 are 4096-bit Random
Access Memories (RAMs), designed with advanced Emitter
Coupled Logic (ECL) circuitry. The devices are organized
as 1024-words-by-4-bits and meet the standard 10K/100K
family signal levels. The SY100474 is also supply voltage-
compatible with 100K ECL, while the SY101474 operates
from 10K ECL supply voltage (–5.2V). All feature on-chip
voltage and temperature compensation for improved noise
margin.
The SY10/100/101474 employ proprietary circuit design
techniques and Synergy’s proprietary ASSET advanced
bipolar technology to achieve extremely fast access, write
pulse width and write recovery times. ASSET uses
proprietary technology concepts to achieve significant
reduction in parasitic capacitance while improving device
packing density. Synergy’s circuit design techniques, coupled
with ASSET, result not only in ultra-fast performance, but
also allow device operation with virtually no soft error
sensitivity and with outstanding device reliability in volume
production.
BLOCK DIAGRAM
*
SA = Sense Amplifier
WA = Write Amplifier
Y-Decoder/Driver
A0
DI0
A4
A1
A2
A3
Memory Cell Array
SA/WA*
SA/WA
SA/WA
SA/WA
DO0 DI1 DO1 DI2 DO2 DI3 DO3
WE
CS
A5
A6
A7
A8
A9
1K x 4 ECL RAM
© 1999 Micrel-Synergy
Rev.: D
Amendment: /1
Issue Date:
December 1999
SY10474-3/4/5/7
SY100474-3/4/5/7
SY101474-3/4/5/7


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