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EM636165VE-7L Datasheet(PDF) 7 Page - Etron Technology, Inc. |
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EM636165VE-7L Datasheet(HTML) 7 Page - Etron Technology, Inc. |
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7 / 74 page  EtronTech 1M x 16 SDRAM EM636165 Preliminary 7 Rev. 1.8 Nov 2001 The read data appears on the DQs subject to the values on the LDQM/UDQM inputs two clocks earlier (i.e. LDQM/UDQM latency is two clocks for output buffers). A read burst without the auto precharge function may be interrupted by a subsequent Read or Write command to the same bank or the other active bank before the end of the burst length. It may be interrupted by a BankPrecharge/ PrechargeAll command to the same bank too. The interrupt coming from the Read command can occur on any clock cycle following a previous Read command (refer to the following figure). CLK COMMAND CAS# latency=1 tCK1, DQ's CAS# latency=2 tCK2, DQ's CAS# latency=3 tCK3, DQ's T0 T 1 T2 T3T4 T5T6 T7T8 READ A READ B NOP NOP NOP NOP NOP NOP NOP DOUT A0 DOUT B0 DOUT B1 DOUT B2 DOUT B3 DOUT A0 DOUT B0 DOUT B1 DOUT B2 DOUT B3 DOUT A0 DOUT B0 DOUT B1 DOUT B2 DOUT B3 Read Interrupted by a Read (Burst Length = 4, CAS# Latency = 1, 2, 3) The LDQM/UDQM inputs are used to avoid I/O contention on the DQ pins when the interrupt comes from a Write command. The LDQM/UDQM must be asserted (HIGH) at least two clocks prior to the Write command to suppress data-out on the DQ pins. To guarantee the DQ pins against I/O contention, a single cycle with high-impedance on the DQ pins must occur between the last read data and the Write command (refer to the following three figures). If the data output of the burst read occurs at the second clock of the burst write, the LDQM/UDQM must be asserted (HIGH) at least one clock prior to the Write command to avoid internal bus contention. READ A NOP NOP NOP NOP WRITE B NOP NOP CLK DQM COMMAND DQ's T0 T 1 T2T3 T4 T5 T6T7 T8 NOP DOUT A0 DINB0 DINB1 DINB2 Must be Hi-Z before the Write Command : "H" or "L" Read to Write Interval (Burst Length ≥ 4, CAS# Latency = 3) |
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