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GS74116TP-8I Datasheet(PDF) 2 Page - GSI Technology |
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GS74116TP-8I Datasheet(HTML) 2 Page - GSI Technology |
2 / 14 page Rev: 2.02 3/2000 2/14 © 1999, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. N GS74116TP/J/U TSOP-II 256K x 16 Pin Configuration 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 A4 A3 A2 A1 A0 CE DQ1 DQ2 DQ3 DQ4 VDD VSS DQ5 DQ6 DQ7 DQ8 WE A15 A14 A13 A5 A6 A7 OE UB LB DQ16 DQ15 DQ14 DQ13 VSS VDD DQ12 DQ11 DQ10 DQ9 NC A8 A9 A10 Top view 21 22 24 23 A12 A11 44 pin TSOP II A17 A16 Memory Array Row Decoder Column Decoder Address Input Buffer Control I/O Buffer A0 CE WE OE DQ1 A17 Block Diagram DQ16 UB _____ LB _____ |
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