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FAN6520BIM Datasheet(PDF) 11 Page - Fairchild Semiconductor |
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FAN6520BIM Datasheet(HTML) 11 Page - Fairchild Semiconductor |
11 / 14 page 11 www.fairchildsemi.com FAN6520B Rev. 1.0.3 Most MOSFET vendors specify QGD and QGS. QG(SW) can be determined as: QG(SW) = QGD + QGS – QTH where QTH is the gate charge required to get the MOS- FET to its threshold (VTH). For the high-side MOSFET, VDS = VIN, which can be as high as 20V in a typical por- table application. Care should also be taken to include the delivery of the MOSFET’s gate power (PGATE) in cal- culating the power dissipation required for the FAN6520B: PGATE = QG × VCC × FSW (17) where QG is the total gate charge to reach VCC. Low-Side Losses Q2, however, switches on or off with its parallel shottky diode conducting, therefore VDS ≈ 0.5V. Since PSW is proportional to VDS, Q2’s switching losses are negligible and we can select Q2 based on RDS(ON) only. Conduction losses for Q2 are given by: PCOND = (1-D) × IOUT 2 × R DS(ON) (18) where RDS(ON) is the RDS(ON) of the MOSFET at the highest operating junction temperature and is the minimum duty cycle for the converter. Since DMIN < 20% for portable computers, (1-D) ≈ 1 produces a conservative result, further simplifying the calculation. The maximum power dissipation (PD(MAX) ) is a function of the maximum allowable die temperature of the low- side MOSFET, the θ J-A, and the maximum allowable ambient temperature rise: θ J-A, depends primarily on the amount of PCB area that can be devoted to heat sinking (see Fairchild app note AN-1029 for SO-8 MOSFET thermal information). t s Q GSW () I DRIVER --------------------- Q GSW () VCC V SP – R DRIVER R GATE + ------------------------------------------------ ------------------------------------------------------ ≈≈ (16) D V OUT V IN -------------- = P D MAX () T J MAX () TA MAX () – θ JA – ------------------------------------------------- = (19) |
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