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MAX5936LB Datasheet(PDF) 9 Page - Maxim Integrated Products |
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MAX5936LB Datasheet(HTML) 9 Page - Maxim Integrated Products |
9 / 23 page -48V Hot-Swap Controllers with VIN Step Immunity and No RSENSE _______________________________________________________________________________________ 9 In a normal power-up GATE cycle, the voltage at VOUT (referenced to VEE) ramps to below 74% of the circuit- breaker threshold voltage, VCB. At this time, the remaining GATE voltage is rapidly pulled up to full enhancement. PGOOD is asserted 1.26ms after GATE is fully enhanced (see Figure 4). If the voltage at VOUT remains above 74% of the VCB (when GATE reaches 90% of full enhance- ment), then a power-up to fault management fault has occurred (see Figure 5). GATE is rapidly pulled to VEE, turning off the power MOSFET and disconnecting the load. PGOOD remains deasserted and the MAX5936/ MAX5937 enter the fault management mode. When the power MOSFET is fully enhanced, the MAX5936/MAX5937 monitor the drain voltage (VOUT) for circuit-breaker and short-circuit faults. The MAX5936/ MAX5937 make use of the power MOSFET’s RDS(ON) as the current-sense resistance to detect excessive current through the load. The short-circuit threshold voltage, VSC, is twice VCB (VSC = 2 x VCB) and is available in 100mV, 200mV, and 400mV thresholds. VCB and VSC are temperature-compensated (increasing with tempera- ture) to track the normalized temperature coefficient of RDS(ON) for typical power MOSFETs. When the load current is increased during full enhance- ment, this causes VOUT to exceed VCB but remains less than VSC, and starts the 1.2ms circuit-breaker glitch rejection timer. At the end of the glitch rejection period, if VOUT still exceeds VCB, the GATE is immediately pulled to VEE (330ns), PGOOD (PGOOD) is deasserted, and the part enters fault management. Alternatively, during full enhancement when VOUT exceeds VSC, there is no glitch rejection timer. GATE is immediately pulled to VEE, PGOOD is deasserted, and the part enters fault management. Figure 3. Load Probe Test During Initial Power-Up 40ms/div VEE 20V/div VLP 20V/div VOUT 20V/div ALL VOLTAGES REFERENCED TO GND Figure 2. GATE Voltage Clamp During Power-Up VIN 20V/div VGATE 1V/div 4ms/div CIN = 100 µF Figure 4. MAX5936 Normal Condition VIN 50V/div VPGOOD 50V/div 40ms/div VGATE 10V/div VOUT 50V/div IIN 2A/div Figure 5. MAX5936 Startup in Fault Condition VIN 50V/div VPGOOD 50V/div 40ms/div VGATE 10V/div VOUT 50V/div IIN 2A/div |
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