IDT72T2098L4BBI datasheet(5/51 Pages) IDT

Part #	IDT72T2098L4BBI

Description	2.5 VOLT HIGH-SPEED TeraSync??DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATION

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Manufacturer	IDT [Integrated Device Technology]

Direct Link	http://www.idt.com

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5

COMMERCIAL AND INDUSTRIAL

TEMPERATURERANGES

IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS

32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10

I W

OW

Write Port Width

Read Port Width

L

x20

L

H

x20

x10

H

L

x10

x20

H

x10

TABLE 1 — BUS-MATCHING CONFIGURATION MODES

NOTE:

1. Pin status during Master Reset.

Figure 1. Single Device Configuration Signal Flow Diagram

(x20, x10) DATA OUT (Q0 - Qn)

(x20, x10) DATA IN (D0 - Dn)

MASTER RESET (

MRS)

READ CLOCK (RCLK)

READ ENABLE (

REN)

OUTPUT ENABLE (

OE)

EMPTY FLAG/OUTPUT READY (

EF/OR)

PROGRAMMABLE ALMOST-EMPTY (

PAE)

WRITE CLOCK (WCLK)

WRITE ENABLE (

WEN)

WRITE SINGLE DATA RATE (

WSDR)

FULL FLAG/INPUT READY (

FF/IR)

PROGRAMMABLE ALMOST-FULL (

PAF)

IDT

72T2098

72T20108

72T20118

72T20128

PARTIAL RESET (

PRS)

FIRST WORD FALL THROUGH (FWFT)

RETRANSMIT (

RT)

5996 drw03

SERIAL ENABLE(

SEN)

INPUT WIDTH (IW)

OUTPUT WIDTH (OW)

SERIAL CLOCK (SCLK)

MARK

READ CHIP SELECT (

RCS)

RCLK ECHO (ERCLK)

REN ECHO (EREN)

WRITE CHIP SELECT (

WCS)

READ SINGLE DATA RATE (

RSDR)

SERIAL OUTPUT (SO)

SERIAL INPUT (SI)

SERIAL READ ENABLE(

SREN)

WSDR

RSDR

Write Port Width

Read Port Width

H

Double Data Rate

H

L

Double Data Rate

Single Data Rate

L

H

Single Data Rate

Double Data Rate

L

Single Data Rate

TABLE 2 — DATA RATE-MATCHING CONFIGURATION MODES

NOTE:

1. Pin status during Master Reset.

2. Data Rate Matching can be used in conjunction with Bus-Matching modes.

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