CY3LV512/010
PRELIMINARY
Document #: 38-03002 Rev. *A
Page 4 of 9
.
Table 1. Pin Configurations
20-pin
PLCC
Name
I/O
Description
2DATA
I/O
Three-state DATA output for configuration. Open-collector bidirectional pin for
programming.
4CLK
I
Clock input. Used to increment the internal address and bit counter for reading and program-
ming.
5WP1
I
WRITE PROTECT (1). Used to protect portions of memory during programming. Disabled
by default due to internal pull-down resistor. This input pin is not used during CPLD loading
operations.
6
RESET /
OE
I
RESET/Output Enable input (when SER_EN is HIGH). A LOW level on both the CE and
RESET/OE inputs enables the data output driver. A HIGH level on RESET/OE resets both the
address and bit counters. The logic polarity of this input is programmable as either RESET/OE
or RESET/OE. Delta39K/Quantum38K CPLDs require this pin to be programmed as
RESET/OE hence this document describes the pin as RESET/OE.
7WP2
I
WRITE PROTECT (2). Used to protect portions of memory during programming. Disabled
by default due to internal pull-down resistor. This input pin is not used during CPLD loading
operations.
8CE
I
Chip Enable input. Used for device selection. A LOW level on both CE and OE enables the
data output driver. A HIGH level on CE disables both the address and bit counters and forces
the device into a low-power standby mode. Note that this pin will not enable/disable the device
in the two-wire Serial Programming Mode (i.e., when SER_EN is LOW).
10
GND
Ground pin. A 0.1
µF decoupling capacitor between V
CC and GND is recommended
14
CEO
O
Chip Enable Output. This signal is asserted LOW on the clock cycle following the last bit read
from the memory. It will stay LOW as long as CE and OE are both LOW. It will then follow CE
until OE goes HIGH. Thereafter, CEO will stay HIGH until the entire EEPROM is read again.
A2
I
Device selection input, A2. This is used to enable (or select) the device during programming
(i.e., when SER_EN is LOW).
15
READY
O
Open collector reset state indicator. Driven LOW during power-up reset, released when
power-up is complete. (Recommend a 4.7 k
Ω pull-up on this pin if used).
17
SER_EN
I
Serial enable must be held High during CPLD loading operations. Bringing SER_EN LOW
enables the two-wire Serial Programming Mode.
20
VCC
+3.3V power supply pin.
Pin Configurations
4
5
6
7
8
18
17
16
15
14
CLK
WP1
RESET/OE
WP2
CE
NC
SER_EN
NC
READY
CEO (A2)
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