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DLO31F-14A2 Datasheet(PDF) 4 Page - Data Delay Devices, Inc. |
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DLO31F-14A2 Datasheet(HTML) 4 Page - Data Delay Devices, Inc. |
4 / 4 page DLO31F Doc #98001 DATA DELAY DEVICES, INC. 4 3/17/98 Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com DELAY LINE AUTOMATED TESTING TEST CONDITIONS INPUT: OUTPUT: Ambient Temperature: 25 oC ± 3oC Load: 1 FAST-TTL Gate Supply Voltage (Vcc): 5.0V ± 0.1V Cload: 5pf ± 10% Input Pulse: High = 3.0V ± 0.1V Threshold: 1.5V (Rising & Falling) Low = 0.0V ± 0.1V Source Impedance: 50 Ω Max. Rise/Fall Time: 3.0 ns Max. (measured between 0.6V and 2.4V ) Pulse Width Low: PWIN = 10 x Clock Period Period: PERIN = 20 x Clock Period NOTE: The above conditions are for test only and do not in any way restrict the operation of the device. C1 OUT TRIG IN TRIG Test Setup DEVICE UNDER TEST (DUT) OSCILLOSCOPE PULSE GENERATOR GB C2 FREQUENCY COUNTER Timing Diagram For Testing TEO PERIN PWIN TFALL TRISE 0.6V 0.6V 1.5V 1.5V 2.4V 2.4V 1.5V 1.5V VIH VIL VOH VOL INPUT SIGNAL OUTPUT SIGNAL |
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