CY7C1359A/GVT71256T18
Document #: 38-05120 Rev. **
Page 4 of 24
Pin Descriptions
BGA Pins
TQFP Pins
Name
Type
Description
4P
4N
2A, 3A, 5A, 6A,
3B, 5B, 2C, 3C,
5C, 6C, 2R, 6R,
2T, 3T, 5T, 6T
37
36
35, 34, 33, 32,
100, 99, 82, 81,
80, 48, 47, 46, 45,
44, 49, 50
A0
A1
A
Input-
Synchronous
Addresses: These inputs are registered and must meet the
set-up and hold times around the rising edge of CLK. The
burst counter generates internal addresses associated with
A0 and A1, during burst cycle and wait cycle.
5L
3G
93
94
WEL
WEH
Input-
Synchronous
Byte Write Enables: A byte write enable is LOW for a WRITE
cycle and HIGH for a READ cycle. WEL controls DQ1–DQ9.
WEH controls DQ10–DQ18. Data I/O are high impedance if
either of these inputs are LOW, conditioned by BWE being
LOW.
4M
87
BWE
Input-
Synchronous
Write Enable: This active LOW input gates byte write opera-
tions and must meet the set-up and hold times around the
rising edge of CLK.
4H
88
GW
Input-
Synchronous
Global Write: This active LOW input allows a full 18-bit
WRITE to occur independent of the BWE and WEn lines and
must meet the set-up and hold times around the rising edge
of CLK.
4K
89
CLK
Input-
Synchronous
Clock: This signal registers the addresses, data, chip en-
ables, write control, and data input enable control input on its
rising edge. All synchronous inputs must meet set-up and
hold times around the clock’s rising edge.
4E
98
CE
Input-
Synchronous
Chip Enable: This active LOW input is used to enable the
device and to gate ADSP.
6B
92
CE2
Input-
Synchronous
Chip Enable: This active LOW input is used to enable the
device.
2B
97
CE2
input-
Synchronous
Chip Enable: This active HIGH input is used to enable the
device.
4F
86
OE
Input
Output Enable: This active LOW asynchronous input enables
the data output drivers.
4G
83
ADV
Input-
Synchronous
Address Advance: This active LOW input is used to control
the internal burst counter. A HIGH on this pin generates wait
cycle (no address advance).
4A
84
ADSP
Input-
Synchronous
Address Status Processor: This active LOW input, along with
CE being LOW, causes a new external address to be regis-
tered and a READ cycle is initiated using the new address.
4B
85
ADSC
Input-
Synchronous
Address Status Controller: This active LOW input causes de-
vice to be deselected or selected along with new external
address to be registered. A READ or WRITE cycle is initiated
depending upon write control inputs.
3R
31
MODE
Input-
Static
Mode: This input selects the burst sequence. A LOW on this
pin selects Linear Burst. A NC or HIGH on this pin selects
Interleaved Burst.
7T
64
ZZ
Input-
Asynchronous
Snooze: This active HIGH input puts the device in low power
consumption standby mode. For normal operation, this input
has to be either LOW or NC (No Connect).
7N
52
DEN
Input-
Synchronous
Data Input Enable: This active LOW input is used to control
the update of data input registers.
6M
53
MATCH
Output
Match Output: MATCH will be HIGH if data in the data input
registers match the data stored in the memory array, assum-
ing MOE being LOW. MATCH will be LOW if data do not
match.
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