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PDU13F-40MC3 Datasheet(PDF) 1 Page - Data Delay Devices, Inc. |
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PDU13F-40MC3 Datasheet(HTML) 1 Page - Data Delay Devices, Inc. |
1 / 5 page PDU13F 3-BIT PROGRAMMABLE DELAY LINE (SERIES PDU13F) data delay devices, inc. 3 FEATURES PACKAGES • Digitally programmable in 8 delay steps 14 13 12 11 10 9 8 1 2 3 4 5 6 7 IN N/C N/C OUT OUT/ EN/ GND VCC N/C N/C N/C A0 A1 A2 PDU13F-xx DIP PDU13F-xxA2 Gull-Wing PDU13F-xxB2 J-Lead PDU13F-xxM Military DIP PDU13F-xxMC3 Military Gull-Wing 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 IN N/C N/C N/C OUT OUT/ EN/ GND VCC N/C N/C N/C A0 A1 A2 N/C • Monotonic delay-versus-address variation • Two separate outputs: inverting & non-inverting • Precise and stable delays • Input & outputs fully TTL interfaced & buffered • 10 T 2L fan-out capability • Fits standard 14-pin DIP socket • Auto-insertable FUNCTIONAL DESCRIPTION The PDU13F-series device is a 3-bit digitally programmable delay line. The delay, TDA, from the input pin (IN) to the output pins (OUT, OUT/) depends on the address code (A2-A0) according to the following formula: TDA = TD0 + TINC * A where A is the address code, TINC is the incremental delay of the device, and TD0 is the inherent delay of the device. The incremental delay is specified by the dash number of the device and can range from 0.5ns through 50ns, inclusively. The enable pin (EN/) is held LOW during normal operation. When this signal is brought HIGH, OUT and OUT/ are forced into LOW and HIGH states, respectively. The address is not latched and must remain asserted during normal operation. PIN DESCRIPTIONS IN Delay Line Input OUT Non-inverted Output OUT/ Inverted Output A2 Address Bit 2 A1 Address Bit 1 A0 Address Bit 0 EN/ Output Enable VCC +5 Volts GND Ground SERIES SPECIFICATIONS DASH NUMBER SPECIFICATIONS Part Number Incremental Delay Per Step (ns) Total Delay Change (ns) PDU13F-.5 .5 ± .3 3.5 ± 1.0 PDU13F-1 1 ± .4 7 ± 1.0 PDU13F-2 2 ± .4 14 ± 1.0 PDU13F-3 3 ± .5 21 ± 1.1 PDU13F-5 5 ± .6 35 ± 1.8 PDU13F-10 10 ± 1.0 70 ± 3.5 PDU13F-15 15 ± 1.3 105 ± 5.3 PDU13F-20 20 ± 1.5 140 ± 7.0 PDU13F-40 40 ± 2.0 280 ± 14.0 PDU13F-50 50 ± 2.5 350 ± 17.5 NOTE: Any dash number between .5 and 50 not shown is also available. • Total programmed delay tolerance: 5% or 1ns, whichever is greater • Inherent delay (TD0): 6ns typical (OUT) 5.5ns typical (OUT/) • Setup time and propagation delay: Address to input setup (TAIS): 6ns Disable to output delay (TDISO): 6ns typ. (OUT) • Operating temperature: 0 ° to 70° C • Temperature coefficient: 100PPM/ °C (excludes TD0) • Supply voltage VCC: 5VDC ± 5% • Supply current: ICCH = 45ma ICCL = 20ma • Minimum pulse width: 20% of total delay 2004 Data Delay Devices Doc #97001 DATA DELAY DEVICES, INC. 1 3/25/04 3 Mt. Prospect Ave. Clifton, NJ 07013 |
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