 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
WCMA2016U4B-FF55 Datasheet(PDF) 5 Page - Weida Semiconductor, Inc. |
|
||||||||||||||||||||||||||||||
WCMA2016U4B-FF55 Datasheet(HTML) 5 Page - Weida Semiconductor, Inc. |
|
|
5 / 12 page  WCMA2016U4B 5 Switching Characteristics Over the Operating Range[8] Parameter Description 55ns 70 ns Min Max Min Max Unit READ CYCLE tRC Read Cycle Time 55 70 ns tAA Address to Data Valid 55 70 ns tOHA Data Hold from Address Change 10 10 ns tACE CE LOW to Data Valid 55 70 ns tDOE OE LOW to Data Valid 25 35 ns tLZOE OE LOW to Low Z [9] 5 5 ns tHZOE OE HIGH to High Z [9, 11] 25 25 ns tLZCE CE LOW to Low Z [9] 10 10 ns tHZCE CE HIGH to High Z [9, 11] 25 25 ns tPU CE LOW to Power-Up 0 0 ns tPD CE HIGH to Power-Down 55 70 ns tDBE BHE / BLE LOW to Data Valid 55 70 ns tLZBE [10] BHE / BLE LOW to Low Z [9] 5 5 ns tHZBE BHE / BLE HIGH to High Z [9, 11] 25 25 ns WRITE CYCLE [12] tWC Write Cycle Time 55 70 ns tSCE CE LOW to Write End 45 60 ns tAW Address Set-Up to Write End 45 60 ns tHA Address Hold from Write End 0 0 ns tSA Address Set-Up to Write Start 0 0 ns tPWE WE Pulse Width 40 50 ns tBW BHE / BLE Pulse Width 50 60 ns tSD Data Set-Up to Write End 25 30 ns tHD Data Hold from Write End 0 0 ns tHZWE WE LOW to High Z [9, 11] 20 25 ns tLZWE WE HIGH to Low Z [9] 5 10 ns Notes: 8. Test conditions assume signal transition time of 5 ns or less, timing reference levels of VCC(typ.) /2, input pulse levels of 0 to V CC(typ.), and output loading of the specified IOL/IOH and 30 pF load capacitance. 9. At any given temperature and voltage condition, t HZCE is less than tLZCE, tHZBE is less than tLZBE, t HZOE is less than tLZOE, and t HZWE is less than tLZWE for any given device. 10. If both byte enables are toggled together this value is 10ns 11. tHZOE, t HZCE, tHZBE, and t HZWE transitions are measured when the outputs enter a high impedance state. 12. The internal write time of the memory is defined by the overlap of WE, CE = VIL , BHE and/or BLE = V IL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write.. |
Similar Part No. - WCMA2016U4B-FF55 |
|
Similar Description - WCMA2016U4B-FF55 |
|
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
