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WCSS0418V1P-166BGC Datasheet(PDF) 1 Page - Weida Semiconductor, Inc. |
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WCSS0418V1P-166BGC Datasheet(HTML) 1 Page - Weida Semiconductor, Inc. |
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1 / 17 page  256K x 18 Synchronous-Pipelined Cache RAM WCSS0418V1P Document #: 38-05247 Revised February 6, 2001 Y7C1327 Features • Supports 100-MHz bus for Pentium and PowerPC™ operations with zero wait states • Fully registered inputs and outputs for pipelined operation • 256K by 18 common I/O architecture • 3.3V core power supply • 2.5V / 3.3V I/O operation • Fast clock-to-output times — 3.5 ns (for 166-MHz device) — 4.0 ns (for 133-MHz device) — 5.5 ns (for 100-MHz device) • User-selectable burst counter supporting Intel Pentium interleaved or linear burst sequences • Separate processor and controller address strobes • Synchronous self-timed writes • Asynchronous Output Enable • JEDEC-standard 100 TQFP pinout • “ZZ” Sleep Mode option and Stop Clock option Functional Description The WCSS0418V1P is a 3.3V, 256K by 18 synchronous-pipe- lined cache SRAM designed to support zero wait state sec- ondary cache with minimal glue logic. The WCSS0418V1P I/O pins can operate at either the 2.5V or the 3.3V level. The I/O pins are 3.3V tolerant when VD- DQ=2.5V. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Max- imum access delay from the clock rise is 3.5 ns (166-MHz device). The WCSS0418V1P supports either the interleaved burst se- quence used by the Intel Pentium processor or a linear burst sequence used by processors such as the PowerPC. The burst sequence is selected through the MODE pin. Accesses can be initiated by asserting either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC) at clock rise. Address advancement through the burst sequence is controlled by the ADV input. A 2-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte write operations are qualified with the four Byte Write Select (BW[1:0]) inputs. A Global Write Enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are conducted with on-chip synchronous self-timed write cir- cuitry. Three synchronous Chip Selects (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank se- lection and output three-state control. In order to provide prop- er data during depth expansion, OE is masked during the first clock of a read cycle when emerging from a deselected state. Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM Corporation. CLK ADV ADSC A[17:0] GW BWE BW 1 BW 0 CE1 CE3 CE2 OE ZZ BURST COUNTER ADDRESS REGISTER OUTPUT REGISTERS INPUT REGISTERS 256KX18 MEMORY ARRAY CLK CLK Q0 Q1 Q D CE CE CLR SLEEP CONTROL 18 18 18 16 16 18 (A[1;0]) 2 MODE ADSP Logic Block Diagram DQ[15:0] DP[1:0] DQ[15:8], DP[1] BYTEWRITE REGISTERS DQ DQ[7:0], DP[0] BYTEWRITE REGISTERS DQ ENABLE CE REGISTER DQ ENABLE DELAY REGISTER DQ CE |
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