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WCSN0436V1P-100AC Datasheet(PDF) 3 Page - Weida Semiconductor, Inc. |
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WCSN0436V1P-100AC Datasheet(HTML) 3 Page - Weida Semiconductor, Inc. |
3 / 14 page WCSN0436V1P Document #: 38-05246 Rev. ** Page 3 of 14 Pin Definitions Pin Number Name I/O Description 50–44, 81–82, 99, 100, 32–37 A[16:0] Input- Synchronous Address Inputs used to select one of the 131,072 address locations. Sampled at the rising edge of the CLK. 96–93 BWS[3:0] Input- Synchronous Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the rising edge of CLK. BWS0 controls DQ[7:0] and DP0, BWS1 controls DQ[15:8] and DP1, BWS2 controls DQ[23:16] and DP2, BWS3 controls DQ[31:24] and DP3. See Write Cycle Description table for details. 88 WE Input- Synchronous Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal must be asserted LOW to initiate a write sequence. 85 ADV/LD Input- Synchronous Advance/Load Input used to advance the on-chip address counter or load a new address. When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be loaded into the device for an access. After being deselected, ADV/LD should be driven LOW in order to load a new address. 89 CLK Input-Clock Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is only recognized if CEN is active LOW. 98 CE1 Input- Synchronous Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2, and CE3 to select/deselect the device. 97 CE2 Input- Synchronous Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device. 92 CE3 Input- Synchronous Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device. 86 OE Input- Asynchronous Output Enable, active LOW. Combined with the synchronous logic block inside the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state, when the device has been deselected. 87 CEN Input- Synchronous Clock Enable Input, active LOW. When asserted LOW the clock signal is recog- nized by the SRAM. When deasserted HIGH the Clock signal is masked. Since deasserting CEN does not deselect the device, CEN can be used to extend the previous cycle when required. 29–28, 25–22, 19–18, 13–12, 9–6, 3–2, 79–78, 75–72, 69–68, 63–62 59–56, 53–52 DQ[31:0] I/O- Synchronous Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by A[16:0] during the previous clock rise of the read cycle. The direction of the pins is controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH, DQ[31:0] are placed in a three-state condition. The outputs are automatically three-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE. 30, 1, 80 51 DP[3:0] I/O- Synchronous Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQ[31:0]. During write sequences, DP0 is controlled by BWS0, DP1 is controlled by BWS1, DP2 is controlled by BWS2, and DP3 is controlled by BWS3. 31 MODE Input Strap pin Mode Input. Selects the burst order of the device. Tied HIGH selects the inter- leaved burst order. Pulled LOW selects the linear burst order. MODE should not change states during operation. When left floating MODE will default HIGH, to an interleaved burst order. 15, 16, 41, 65, 66, 91 VDD Power Supply Power supply inputs to the core of the device. Should be connected to 3.3V power supply. 4, 11, 14, 20, 27, 54, 61, 70, 77 VDDQ I/O Power Supply Power supply for the I/O circuitry. Should be connected to a 3.3V power supply. |
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