ASAHI KASEI

[AK4555]

MS0363-E-01

2005/08

- 11 -

Power-down & Reset

The ADC and DAC of AK4555 are placed in the power-down mode by bringing each power down pin, PWADN,

PWDAN = “L” independently and each digital filter is also reset at the same time. These resets should always be done

after power-up. In case of the ADC, an anlog initialization cycle starts after exiting the power-down mode. Therefore, the

output data, SDTO becomes available after 2081 cycles of LRCK clock. This initialization cycle does not affect the DAC

operation. Figure 5 shows the power-up sequence when the ADC is powered up before the DAC power-up.

Idle Noise

The clocks may be stopped.

ADC Internal

State

PWADN

2081/fs

Normal Operation

Power-down

Init Cycle

Normal Operation

GD

GD

Clock In

MCLK,LRCK,SCLK

ADC In

(Analog)

Idle Noise

“0”data

ADC Out

(Digital)

PWDAN

Normal Operation

Power-down

Normal Operation

DAC Internal

State

“0”data

DAC In

(Digital)

DAC Out

(Analog)

GD

External

Mute

Mute ON

GD

Figure 5. Power-up Sequence