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AKD5359 Datasheet(PDF) 7 Page - Asahi Kasei Microsystems |
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AKD5359 Datasheet(HTML) 7 Page - Asahi Kasei Microsystems |
7 / 18 page ASAHI KASEI [AK5359] MS0428-E-00 2005/09 - 7 - DC CHARACTERISTICS (Ta=Tmin ∼ Tmax ; VA=4.5 ∼ 5.5V; VD=3.0 ∼ 5.5V) Parameter Symbol min typ max Units High-Level Input Voltage Low-Level Input Voltage VIH VIL 70%VD - - - - 30%VD V V High-Level Output Voltage (Iout= −1mA) Low-Level Output Voltage (Iout=1mA) VOH VOL VD −0.5 - - - - 0.5 V V Input Leakage Current Iin - - ±10 µA SWITCHING CHARACTERISTICS (Ta=Tmin ∼ Tmax ; VA=4.5 ∼ 5.5V; VD=3.0 ∼ 5.5V; C L=20pF) Parameter Symbol min typ max Units Master Clock Timing Frequency Pulse Width Low Pulse Width High fCLK tCLKL tCLKH 2.048 0.4/fCLK 0.4/fCLK 41.472 MHz ns ns LRCK Frequency fs 8 216 kHz Duty Cycle Slave mode Master mode 45 50 55 % % Audio Interface Timing Slave mode SCLK Period SCLK Pulse Width Low Pulse Width High LRCK Edge to SCLK “ ↑” (Note 10) SCLK “ ↑” to LRCK Edge (Note 10) LRCK to SDTO (MSB) (Except I 2S mode) SCLK “ ↓” to SDTO tSCK tSCKL tSCKH tLRSH tSHLR tLRS tSSD 72 33 33 20 20 25 25 ns ns ns ns ns ns ns Master mode SCLK Frequency SCLK Duty SCLK “ ↓” to LRCK SCLK “ ↓” to SDTO fSCK dSCK tMSLR tSSD −20 −20 64fs 50 20 20 Hz % ns ns Reset Timing PDN Pulse Width (Note 11) PDN “ ↑” to SDTO valid at Slave Mode (Note 12) PDN “ ↑” to SDTO valid at Master Mode (Note 12) tPD tPDV tPDV 150 4132 4129 ns 1/fs 1/fs Note 10. SCLK rising edge must not occur at the same time as LRCK edge. Note 11. The AK5359 can be reset by bringing the PDN pin = “L”. Note 12. This cycle is the number of LRCK rising edges from the PDN pin = “H”. |
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