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AZ7025ZTR-E1 Datasheet(PDF) 9 Page - BCD Semiconductor Manufacturing Limited |
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AZ7025ZTR-E1 Datasheet(HTML) 9 Page - BCD Semiconductor Manufacturing Limited |
9 / 12 page AZ70XX Preliminary Datasheet 9 Jul. 2005 Rev. 1. 3 BCD Semiconductor Manufacturing Limited VOLTAGE DETECTOR AZ70XX Figure 13. Low Voltage Indicator Figure 14. CPU Resetting Circuit 1 3 2 V CC AZ70XX OUT GND LED V CC R1 220 V CC +5V R1 3.3k 1 3 2 V CC AZ70XX OUT GND CPU V CC GND RESET C1 1 µF + Figure 12 is a typical timing waveform for AZ70XX during power-up and temporary power-down period. Here is some explanations for AZ70XX's operation. 1. During power-up period, VOUT will remain undefined until VCC rises above VOPR (typically 0.8V). After that moment, the output will become valid and will be at its logic low state while VOPR<VCC<VS for power-up operating. 2. After a delay time of tpLH from the moment VCC>VS, the VOUT will be at its logic high state. In general, VOUT is dependent upon the voltage that the pull up resistor connected to. 3. During power-down, after a delay time of tpHL from the moment VCC<VS-VHYS, VOUT will be at its logic low state. In general, at rated output current and VCC, VOUT can be pulled down to a voltage as low as within 0.4V from GND. (See the Electrical Characteristics section). 4. VOUT will be at its logic low state while VS- VHYS>VCC>VOPR for power-down operating. 5. After VCC falls below VOPR, the output is undefined. Operating Diagram (Continued) Typical Applications |
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