1

2

3

4

5

6

7

8

9

10

11

12

IS61C64B

Rev. D

07/01/02

–10ns

-12ns

-15ns

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

Write Cycle Time

10

—

12

—

15

—

ns

CE to Write End

9

—

10

—

12

—

ns

Address Setup Time to Write End

9

—

10

—

12

—

ns

Address Hold from Write End

0

—

0

—

0

—

ns

Address Setup Time

0

—

0

—

0

—

ns

WE Pulse Width

8

—

8

—

10

—

ns

Data Setup to Write End

8

—

8

—

9

—

ns

Data Hold from Write End

0

—

0

—

0

—

ns

—

6

—

6

—

7

ns

0

—

0

—

0

—

ns

Notes:

1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and

output loading specified in Figure 1a.

2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

3. The internal write time is defined by the overlap of

CE LOW and WE LOW. All signals must be in valid states to initiate a Write,

but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling

edge of the signal that terminates the write.