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DAC7821 Datasheet(PDF) 4 Page - Texas Instruments

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Part # DAC7821
Description  12-Bit, Parallel Input, Multiplying Digital-to-Analog Converter
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

DAC7821 Datasheet(HTML) 4 Page - Texas Instruments

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DATA VALID
DATA VALID
R/W
CS
DATA
t
1
t
2
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
TIMING REQUIREMENTS: 2.5 V to 4.5 V
TIMING REQUIREMENTS: 4.5 V to 5.5 V
DAC7821
SBAS365A – OCTOBER 2005 – REVISED FEBRUARY 2006
TIMING INFORMATION
At t
r = tf = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2; VDD = +2.5 V to +4.5 V, VREF = +10 V,
I
OUT2 = 0 V. All specifications –40°C to +125°C, unless otherwise noted.
DAC7821
PARAMETER(1)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t1
R/W to CS setup time
0
ns
t2
R/W to CS hold time
0
ns
t3
CS low time (write cycle)
10
ns
t4
Data setup time
6
ns
t5
Data hold time
0
ns
t6
R/W high to CS low
5
ns
t7
CS min high time
9
ns
t8
Data access time
20
40
ns
t9
Bus relinquish time
5
10
ns
(1)
Ensured by design; not production tested.
At t
r = tf = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2; VDD = +4.5 V to +5.5 V, VREF = +10 V,
I
OUT2 = 0 V. All specifications –40°C to +125°C, unless otherwise noted.
DAC7821
PARAMETER(1)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t1
R/W to CS setup time
0
ns
t2
R/W to CS hold time
0
ns
t3
CS low time (write cycle)
10
ns
t4
Data setup time
6
ns
t5
Data hold time
0
ns
t6
R/W high to CS low
5
ns
t7
CS min high time
7
ns
t8
Data access time
10
20
ns
t9
Bus relinquish time
5
10
ns
(1)
Ensured by design; not production tested.
4


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