Detailed Description

LVDS is a signaling method intended for point-to-point

communication over a controlled-impedance medium

as defined by the ANSI TIA/EIA-644 and IEEE 1596.3

standards. LVDS uses a lower voltage swing than other

common communication standards, achieving higher

data rates with reduced power consumption while

reducing EMI and system susceptibility to noise.

The MAX9173 is a 500Mbps, four-channel LVDS receiv-

er intended for high-speed, point-to-point, low-power

applications. Each channel accepts an LVDS input and

translates it to an LVTTL/LVCMOS output. The receiver

is specified to detect differential signals as low as

100mV and as high as 1.2V within an input voltage

put of an LVDS driver is nominally centered around a

1.2V offset. This offset, coupled with the receiver’s 0 to

the signal (as seen by the receiver). This allows for a

difference in ground references of the transmitter and

the receiver, the common-mode effects of coupled

noise, or both.

Quad LVDS Line Receiver with Flow-Through

Pinout and “In-Path” Fail-Safe

6

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PIN

TSSOP/SO

QFN

NAME

FUNCTION

1

15

IN1-

Inverting Differential Receiver Input for Receiver 1

2

16

IN1+

Noninverting Differential Receiver Input for Receiver 1

3

1

IN2+

Noninverting Differential Receiver Input for Receiver 2

4

2

IN2-

Inverting Differential Receiver Input for Receiver 2

5

3

IN3-

Inverting Differential Receiver Input for Receiver 3

6

4

IN3+

Noninverting Differential Receiver Input for Receiver 3

7

5

IN4+

Noninverting Differential Receiver Input for Receiver 4

8

6

IN4-

Inverting Differential Receiver Input for Receiver 4

9, 16

7, 14

EN, EN

Receiver Enable Inputs. When EN = high and EN = low or open, the outputs are active.

For other combinations of EN and EN, the outputs are disabled and in high

impedance.

10

8

OUT4

LVCMOS/LVTTL Receiver Output for Receiver 4

11

9

OUT3

LVCMOS/LVTTL Receiver Output for Receiver 3

12

10

GND

Ground

13

11

Place the smaller value cap as close to the pin as possible.

14

12

OUT2

LVCMOS/LVTTL Receiver Output for Receiver 2

15

13

OUT1

LVCMOS/LVTTL Receiver Output for Receiver 1

—

Exposed Pad

EP

Exposed Pad. Solder to ground plane for proper heat dissipation.

Pin Description

ENABLES

INPUTS

OUTPUT

EN

EN

(IN_+) - (IN_-)

OUT_

≥ 0H

≤ -100mV

L

H

L or open

Open, undriven short, or undriven parallel termination

H

All other combinations of ENABLE pins

Don’t care

Z

Table 1. Input/Output Function Table