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LTABF Datasheet(PDF) 3 Page - Linear Technology |
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LTABF Datasheet(HTML) 3 Page - Linear Technology |
3 / 16 page LTC4300A-1/LTC4300A-2 3 sn4300a12 4300a12fs Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired Note 2: IPULLUPAC varies with temperature and VCC voltage, as shown in the Typical Performance Characteristics section. Note 3: The connection circuitry always regulates its output to a higher voltage than its input. The magnitude of this offset voltage as a function of the pullup resistor and VCC voltage is shown in the Typical Performance Characteristics section. ELECTRICAL CHARACTERISTICS The q denotes the specifications which apply over the full operating temperature range, otherwise specfications are at TA = 25°C. VCC = 2.7V to 5.5V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Rise-Time Accelerators IPULLUPAC Transient Boosted Pull-Up Current Positive Transition on SDA,SCL, VCC = 2.7V, 1 2 mA Slew Rate = 1.25V/ µs (Note 2), LTC4300A-2, ACC = 0.7 • VCC2, VCC2 = 2.7V VACCDIS Accelerator Disable Threshold LTC4300A-2 0.3 • VCC2 0.5 • VCC2 V VACCEN Accelerator Enable Threshold LTC4300A-2 0.5 • VCC2 0.7 • VCC2 V IVACC ACC Input Current LTC4300A-2 ±0.1 ±1 µA tPDOFF ACC Delay, On/Off LTC4300A-2 5 ns Input-Output Connection VOS Input-Output Offset Voltage 10k to VCC on SDA, SCL, VCC = 3.3V (Note 3), q 0 100 175 mV LTC4300A-2, VCC2 = 3.3V, VIN = 0.2V fSCL, SDA Operating Frequency Guaranteed by Design, Not Subject to Test 0 400 kHz CIN Digital Input Capacitance Guaranteed by Design, Not Subject to Test 10 pF VOL Output Low Voltage, Input = 0V SDA, SCL Pins, ISINK = 3mA, VCC = 2.7V, q 0 0.4 V VCC2 = 2.7V, LTC4300A-2 ILEAK Input Leakage Current SDA, SCL Pins = VCC = 5.5V, ±5 µA LTC4300A-2, VCC2 = 5.5V Timing Characteristics fI2C I2C Operating Frequency (Note 4) 0 400 kHz tBUF Bus Free Time Between Stop (Note 4) 1.3 µs and Start Condition thD,STA Hold Time After (Repeated) (Note 4) 0.6 µs Start Condition tsu,STA Repeated Start Condition Setup Time (Note 4) 0.6 µs tsu,STO Stop Condition Setup Time (Note 4) 0.6 µs thD, DAT Data Hold Time (Note 4) 300 ns tsu, DAT Data Setup Time (Note 4) 100 ns tLOW Clock Low Period (Note 4) 1.3 µs tHIGH Clock High Period (Note 4) 0.6 µs tf Clock, Data Fall Time (Notes 4, 5) 20 + 0.1 • CB 300 ns tr Clock, Data Rise Time (Notes 4, 5) 20 + 0.1 • CB 300 ns Note 4: Guaranteed by design, not subject to test. Note 5: CB = total capacitance of one bus line in pF. |
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